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参数资料
| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 3/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
Pin Description
NAME
VCC
GND
IIN9-0
QIN9-0
SYNC
COF
COFSYNC
SOF
SOFSYNC
A2-0
C7-0
WR
RD
FZ_ST
FZ_CT
LKINT
THRESH
SLOCLK
ISER
QSER
SSYNC
SERCLK
AOUT9-0
BOUT9-0
SMBLCLK
TYPE
-
-
I
I
I
O
O
O
O
I
I/O
I
I
I
I
O
O
O
I
I
I
I
O
O
O
DESCRIPTION
+5V Power Supply.
Ground.
In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 15). These inputs are
sampled by CLK when the SYNC signal is active Low. IIN9 is the MSB. See “Input Controller” on page 6.
Quadrature Parallel Input. Data may be two’s complement or offset binary format (see Table 15). These inputs are
sampled by CLK when the SYNC signal is active Low. QIN9 is the MSB. “Input Controller” on page 6.
Data Sync. When SYNC is asserted “Low”, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the
rising edge of CLK.
Carrier Offset Frequency. The frequency term generated by the Carrier Tracking Loop Filter is output serially via this
pin. The new offset frequency is shifted out MSB first by CLK or SLOCLK starting with the clock cycle after the
assertion of COFSYNC.
Carrier Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data
word. (Programmable Polarity, see Table 42 on page 42, Bit 11).
Sampler Offset Frequency. Sample frequency correction term generated by the Symbol Tracking Loop Filter is
output serially via this pin. The frequency word is shifted out MSB first by CLK or SLOCLK starting with the clock
cycle after assertion of SOFSYNC.
Sampler Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data
word. (Programmable Polarity, see Table 42 on page 42, Bit 12).
Address Bus. The address on these pins specify a target register for reading or writing (see “Microprocessor
Interface” on page 27). A0 is the LSB.
Microprocessor Interface Data Bus. This bi-directional bus is used for reading and writing to the processor interface.
These are the data I/O pins for the processor interface. C0 is the LSB.
Write. This is the write strobe for the processor interface (see “Microprocessor Interface” on page 27).
Read. This is the read enable for the processor interface (see “Microprocessor Interface” on page 27).
Freeze Symbol Tracking Loop. Asserting this pin “high” zeroes the sampling error into the Symbol Tracking Loop
Filter (see “Symbol Tracking Loop Filter” on page 17).
Freeze Carrier Tracking Loop. Asserting this pin “high” zeroes the carrier Phase Error input to the Carrier Tracking
Loop Filter.
Lock Detect Interrupt. This pin is asserted “high” for at least 4 CLK cycles when the Lock Detector Integration cycle
is finished (see “Lock Detector” on page 23). Used as an interrupt for a processor. The Lock Detect Interrupt may
be asserted “high” longer than 4 CLK cycles, depending on the Lock Detector mode.
Threshold Exceeded. This output is asserted “low” when the magnitude out of the Cartesian to Polar converter
exceeds the programmable Power Detect Threshold (see Table 16 on page 33 and “AGC” on page 10).
Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The
clock is programmable and has a 50% duty cycle. Note: Not used when the HSP50110 is used with the HSP50210
(see Table 42 page 42).
In-Phase Serial Input. Serial data input for In-Phase Data. Data on this pin is shifted in MSB first and is synchronous
to SERCLK (see “Input Controller” on page 6).
Quadrature Serial Input. Serial data input for Quadrature Data. Data on this pin is shifted in MSB first and is
synchronous to SERCLK (see “Input Controller” on page 6).
Serial Word Sync. This input is asserted “high” one CLK before the first data bit of the serial word (see Figure 2).
Serial Clock. May be asynchronous to other clocks. Used to clock in serial data (see “Input Controller” on page 6).
A Output. Data on this output depend on the configuration of Output Selector. AOUT9 is the MSB (see Table 43 on
page 44).
B Output. Data on this output depend on the configuration of Output Selector. BOUT9 is the MSB (see Table 43 page 44).
Symbol Clock. 50% duty cycle clock aligned with soft bit decisions (see Figure 19).
3
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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