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参数资料
| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 31/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
WR
RD
A0-2
C0-7
5
3
3
PE MSW
2
PE LSW
1
FL MSW
0
FL LSW
4
30
4
25
CLK
SR-7
LKINT
1
2
3
4
5
6
5
6
5
6
5
7
8
9
10
NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in “Waveforms” on page 50 to ensure proper operation. The Processor waveforms are not
required to be synchronous to CLK. They are shown that way to clarify the illustration.
1. LKINT Asserts Indicating End of Lock Detector Accumulation Cycle; Accumulators Ready to Read.
2. Set A0-2 to 5 for Reading Lock Detector.
3. Load Read Address Register with 3 dec to enable the Lock Detector Phase Error Accumulator for Reading.
4. Set A0-2 to 3 for Phase Error (PE) Read.
5. Assert RD and read (Phase Error (PE) MSW; PE LSW; False Lock (FL) MSW; FL LSW).
6. Change Read Address to (2; 1; 0) to read various Lock Detection values.
7. Change Address to 4 to Initialize the Lock Detector.
8. Load Write Address Register with 30 dec to initialize the Lock Detector Accumulators and Reset Integration Counters. (Only has
an effect in μP mode).
9. Keep Address to 4 to Restart the Lock Detector.
10. Load Write Address Register with 25 dec to restart the Lock Detector. (Only necessary if not in the μP mode).
FIGURE 24. PROCESSOR INTERRUPT MONITOR/LOCK DETECTOR READ
.
CLK
RD
A0-2
4
C7-0
STATUS CAN CHANGE EVERY CLK
FIGURE 25. INTERNAL STATUS REGISTER READ
31
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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