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参数资料
| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 34/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
TABLE 18. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 3
BIT
POSITION
5-2
1-0
FUNCTION
Phase Offset
Shift Factor
DESCRIPTION
These bits set the phase offset added (modulo 2 π ) to the phase output of the Cartesian-to-Polar
Converter. The phase offset is represented as a 4-bit fractional 2’s Complement value with the following
binary format:
Phase Offset = -2 0 . 2 -1 2 -2 2 -3.
This format provides a range from 0.875 to -1 (0111 to 1000) which corresponds to phase offset settings
from 7 π /8 to - π respectively. Resolution of 22.5° is provided. Bit position 5 is the MSB.
The bits set the left shift required by the Carrier Phase Error Detector. These two bits specify a left shift
of 0, 1, 2 or 3 places. MSBs are discarded and LSBs are zero-filled. Bit 1 is the MSB.
TABLE 19. FREQUENCY DETECTOR CONTROL REGISTER
DESTINATION ADDRESS = 4
BIT
POSITION
31-8
7-3
2-0
FUNCTION
Not Used
Reserved
Discriminator Delay
DESCRIPTION
No programming required.
Reserved. Set to 0 for proper operation.
The frequency detector (discriminator) computes frequency by subtracting a delayed phase term from
the current phase term (d θ /dt). A programmable delay is used to set the discriminator gain. These bits
set the delay as given by:
Delay = 2 K ,
where K is the 3-bit value programmed here. Delays of 1, 2, 4, 8, and 16 are possible.
TABLE 20. FREQUENCY ERROR DETECTOR CONTROL REGISTER
DESTINATION ADDRESS = 5
BIT
POSITION
31-8
7-3
2-0
FUNCTION
Not Used
Frequency Offset
Shift Factor
DESCRIPTION
No programming required.
These bits set the frequency offset added (modulo) to the frequency output of the discriminator. The frequency
offset is represented as a 5-bit fractional 2’s complement value with the following binary format:
Frequency Offset = -2 0 . 2 -1 2 -2 2 -3 2 -4.
This format provides a range from 0.9375 to -1.0 (0111 to 1000). The range and resolution of the
frequency offset depend on the discriminator delay and input rate. The frequency offset is added to the
5 MSBs of the discriminator output. Note: Set the frequency offset to 0 when using frequency aided
acquisition with PSK waveforms.
These bits set the left shift required by the Frequency Error Detector. These two bits set a left shift of 0,
1, 2, 3, or 4 places. Bit 2 is the MSB. Values greater than 4 are invalid. Note: Set the shift factor to 0 when
using frequency aided acquisition with PSK waveforms.
TABLE 21. CARRIER LOOP FILTER CONTROL REGISTER #1
DESTINATION ADDRESS = 6
BIT
POSITION
31-8
7
6
FUNCTION
Not Used
Reserved
Lead/Lag to Serial
Output Routing
34
DESCRIPTION
No programming required.
Reserved. Set to 0 for proper operation.
0 = The Carrier Loop Filter ’s Lag Accumulator is routed to the Serial Output Controller.
1 = The lead and lag paths in the Carrier Loop Filter are summed and routed to the Serial Output
Controller.
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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