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| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 40/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
TABLE 35. LOCK DETECTOR CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 20
BIT
POSITION
31-28
27
FUNCTION
Reserved
False Lock
DESCRIPTION
Reserved. Set to 0 for proper operation.
This bit selects the input to the False Lock Accumulator.
Accumulator Operation 0 = Frequency Error input enabled to accumulator.
1 = False Lock Bit enabled to accumulator.
26-20
19-10
9-0
Dwell Counter
Pre-load
Integration Counter
Pre-Load
(Acquisition)
Integration Counter
The Dwell Counter holds off the Lock Accumulator integration for the number of integration cycles
programmed here. The length of the integration cycle is set in the bit positions 19-10. The 7-bit value
programmed here should be set to 1 less than the desired hold off time in integration cycles. The pre-load
is zeroed during Track Mode. Only used during stepped acquisition mode.
The Integration Counter controls the number Phase Error samples accumulated by the Lock
Accumulator. The 10-bit number loaded here is set to two less than the number of Phase Error samples
desired in the Integration Period. Total Range 2 to 1025. Bit 19 is the MSB.
Function is identical to Acquisition Integration Counter Pre-Load. See previous.
Pre-Load (Track)
TABLE 36. LOCK ACCUMULATOR PRE-LOADS CONTROL REGISTER
DESTINATION ADDRESS = 21
BIT
POSITION
FUNCTION
DESCRIPTION
31-16
Lock Accumulator Pre- The lock threshold is set by an accumulator pre-load which is backed off from the accumulator full scale
Load
(Acquisition)
by the threshold amount. The Lock Accumulator is 18 bits and the accumulator bit weightings relative to
the magnitude of the Phase Error input and the pre-load is as follows:
BIT WEIGHTING OF ACCUMULATOR PRE-LOAD
2 10 2 9 2 8 2 7 ......2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7
BINARY POINT
BIT WEIGHTING OF
PHASE ERROR MAGNITUDE
The accumulator roll over is at the 2 11 bit position.
15-0
Lock Accumulator Pre- Function is identical to Acquisition Lock Accumulation Pre-Load. See previous.
Load (Track)
TABLE 37. FALSE LOCK ACCUMULATOR PRE-LOAD CONTROL REGISTER
DESTINATION ADDRESS = 22
BIT
POSITION
31-16
FUNCTION
False Lock
Accumulator
Pre-Load (Acquisition)
DESCRIPTION
Depending on configuration, the input to the False Lock Accumulator is either the false lock indicator bit
or the magnitude of the frequency error detector output. Like the Lock Accumulator, the threshold is set
by an accumulator pre-load that is backed off from accumulator full scale. The False Lock Accumulator
can accumulate sums up to 18 bits, and the bit weightings of the false lock indicator bit and the frequency
error input relative to accumulator full scale are shown as follows.
BIT WEIGHTING OF ACCUMULATOR PRE-LOAD
2 10 2 9 2 8 2 7 ......2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7
BIT WEIGHTING OF
BINARY POINT
BIT WEIGHTING OF
FREQUENCY ERROR MAGNITUDE
FALSE LOCK INDICATOR BIT
The accumulator roll over is at the 2 11 bit position.
15-0
False Lock
Accumulator
Pre-Load (Track)
40
See previous. The Lock Detector State Machine only uses the accumulator during the verify state during
which the Track parameters are used.
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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