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| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 32/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
TABLE 15. DATA PATH CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 0
BIT
POSITION
31-27
26-24
23-16
FUNCTION
Reserved
Integrate/Dump Shifter
Gain
Input Level Detector
Threshold
DESCRIPTION
Reserved. Set to 0 for proper operation.
These bits set the shifter attenuation in the Integrate/Dump Filter.
000 = No Shift (Gain = 2 0 ).
001 = Right Shift 1 (Gain = 2 -1 ).
010 = Right Shift 2 (Gain = 2 -2 ).
011 = Right Shift 3 (Gain = 2 -3 ).
100 = Right Shift 4 (Gain = 2 -4 ).
Other Codes are invalid.
This register sets the magnitude threshold for the Input Level Detector (see “Input Level Detector” on
page 6). This 8-bit value is a fractional unsigned number whose format is given by:
2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 .
The possible threshold values range from 0 to 1.9961 (00 - FF hex). The magnitude range for complex
inputs is 0.0 to 1.4142 while that for real inputs range is 0.0 to 1.0. Note: The algorithm used to estimate
threshold produces a maximum output of 1.375, therefore a threshold of greater than 1.375 will never
be exceeded.
15
Input Data Format Select 0 = Two’s Complement Input.
1 = Offset binary Input.
14
13
12
11
10
9
8
7
6
5
4-1
0
Serial/Parallel Input
Select
Input Level Detector
Output Select
Q Input to Complex
Multiplier
I Input to Complex
Multiplier
Complex Multiplier
Bypass
Demodulation/Loop
Filter Mode
Select
Cartesian/Polar Input
Select
RRC Filter Enable
Integrate and Dump
Filter Test Mode
Integrate and Dump
Input Select
Integrate and Dump
Decimation Select
OQPSK Data
De-Skew Select
32
0 = Parallel Input.
1 = Serial Input.
0 = HI/LO output of 1 means input ≤ threshold.
1 = HI/LO output of 1 means input > threshold.
0 = QIN9-0 enabled to Complex Multiplier.
1 = Q input to Complex Multiplier zeroed.
0 = IIN9-0 enabled to Complex Multiplier.
1 = I input to complex multiplier set to negative full scale (200 Hex).
0 = Data enabled to Complex Multiplier (Multiplied by output of NCO).
1 = Complex Multiplier Bypassed.
0 = Error detector outputs routed to Loop Filters (Normal Mode of Operation).
1 = Part functions as dual Loop Filters. The IIN9-0 input is routed to the Symbol Loop Filter; the
QIN9-0 input is routed to the Carrier Loop Filter. Data is gated into the Loop Filters with the assertion
of SYNC.
0 = Enable output of AGC Multiplier to Cartesian to Polar Converter.
1 = Enable output of Integrate and Dump Filter to the Cartesian to Polar Converter.
0 = Enable RRC filter.
1 = Bypass RRC filter.
0 = End-Symbol Samples routed to Output Formatter.
1 = Both End and Mid Symbol routed to Output Formatter: End-symbol samples occur when
SMBLCLK is high; Mid-Symbol samples occur when SMBLCLK is low.
0 = Input taken from output of Frequency Discriminator (FSK routing).
1 = Input taken from output of AGC Multiplier (Select this setting for PSK demodulation).
Bit 4 is the MSB.
1000 = No Decimation (no accumulation, no sample pair summing).
0000 = Decimation by 2 (no accumulation, sample pair summing).
0001 = Decimation by 4 (accumulate 2 samples, sample pair summing).
0010 = Decimation by 8 (accumulate 4 samples, sample pair summing).
0011 = Decimation by 16 (accumulate 8 samples, sample pair summing).
0100 = Decimation by 32 (accumulate 16 samples, sample pair summing).
All other codes are invalid.
0 = Disables Q channel data delay.
1 = Delays Q Channel by 1/2 Symbol time to remove OQPSK stagger.
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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