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参数资料
| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 38/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
TABLE 29. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 14
BIT
POSITION
8
7-3
2
1
0
FUNCTION
Single/Double Rail
Sampling Error
Sampling Error
Accumulation
Lead Sampling Error
Enable
Lag Sampling Error
Enable
Invert Sampling Error
DESCRIPTION
This bit sets whether sampling error is derived from symbol transitions on just the I rail (single rail) or both
the I and Q rails (dual rail). In single rail operation sampling error from the Q rail is nulled and only the I rail
is used. In dual rail operation the sampling error from both the I an Q rails is summed and then scaled by
one half.
0 = Dual Rail Operation.
1 = Single Rail Operation.
Note: Set to 1 for BPSK operation and 0 for QPSK operation.
These bits set the number of sampling error measurements to accumulate before running the Symbol Loop
Filter. The loop filter requires 8 CLKs to compute an output. The sampling error detector generates error
terms at the symbol rate. Thus, the error accumulator must be used if the symbol rate exceeds 1/8 CLK to
ensure that no error terms are missed (see “Sampling Error Detector” on page 17). The 5-bit value
programmed here is set to one less than the desired number of error terms to accumulate. For example,
setting these bits to 00011 (BINARY) would cause 4 error terms to be accumulated. A total range from 1 to
32 is provided.
0 = Sampling error enabled to lead path of loop filter.
1 = Sampling error to lead path of loop filter zeroed.
0 = Sampling error enabled to lag path of loop filter.
1 = Sampling error to lag path of loop filter zeroed (First Order Loop).
0 = Sampling error normal.
1 = Sampling error inverted.
TABLE 30. SYMBOL TRACKING LOOP FILTER UPPER LIMIT CONTROL REGISTER
DESTINATION ADDRESS = 15
BIT
POSITION
31-0
FUNCTION
Symbol Tracking
Loop Filter Upper
Limit
DESCRIPTION
The 32-bit two’s complement value programmed here sets the upper tracking limit of the Symbol Tracking Loop
Filter by setting the upper limit of the loop filter’s lag accumulator. If the limit is exceeded, the upper 32 bits of the
40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
TABLE 31. SYMBOL TRACKING LOOP FILTER LOWER LIMIT CONTROL REGISTER
DESTINATION ADDRESS = 16
BIT
POSITION
31-0
FUNCTION
Symbol Tracking
Loop Filter Lower
Limit
DESCRIPTION
The 32-bit two’s complement value programmed here sets the Lower tracking limit of the Symbol Tracking Loop
Filter by setting the lower limit of the loop filter’s lag accumulator. If the running sum falls below the limit, the upper
32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER
DESTINATION ADDRESS = 17
BIT
POSITION
31-24
23-18
17-14
FUNCTION
Not Used
Reserved
Symbol Tracking
Lead Gain Mantissa
(Acquisition)
38
DESCRIPTION
No programming required.
Reserved. Set to 0 for proper operation.
These bits are the 4 fractional bits of the lead gain mantissa shown as follows:
Symbol Tracking Lead Gain Mantissa = 01. 2 -1 2 -2 2 -3 2 -4.
This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary.
Bit position 17 is the MSB.
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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