- 您现在的位置：买卖IC网 > PDF目录18822 > HSP50214BVCZ (Intersil)IC DOWNCONVERTER 14BIT 120-MQFP PDF资料下载
参数资料
| 型号： | HSP50214BVCZ |
| 厂商： | Intersil |
| 文件页数： | 20/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
HSP50214B
Additionally, the Programmable FIR filter provides for
decimation factors, R, from 1 to 16. The processing rate of
the Filter Compute Engine is PROCCLK. As a result, the
frequency of PROCCLK must exceed a minimum value to
ensure that a filter calculation is complete before the result is
required for output. In configurations which do not use
decimation, one input sample period is available for filter
C0
CN-1
COEFFICIENT
NUMBER
EVEN SYMMETRIC
EVEN TAP FILTER
C0
CN-1
COEFFICIENT
NUMBER
ODD SYMMETRIC
calculation before an output is required. For configurations
which employ decimation, up to 16 input sample periods
EVEN TAP FILTER
may be available for filter calculation.
C0
CN-1
C0
CN
For real filter configurations, use Equations 11A and 11B to
calculate the number of taps available at a given input filter
sample rate.
EVEN SYMMETRIC
ODD TAP FILTER
COEFFICIENT
NUMBER
ODD SYMMETRIC
ODD TAP FILTER
COEFFICIENT
NUMBER
TAPS = ( floor [ PROCCLK ? ( F SAMP ? R ) – R ] ) ( 1 +
SYM) – [ ( SYM ) ( ODD# ) ]
(EQ. 11A)
for real filters, and
C0
CN-1
COEFFICIENT
NUMBER
C0
CN-1
COEFFICIENT
NUMBER
TAPS = floor [ (PROCCLK ? ( F SAMP ? R ) – R ) ? 2]
(EQ. 11B)
ASYMMETRIC
EVEN TAP FILTER
ASYMMETRIC
ODD TAP FILTER
REAL FILTERS
for complex filters, where floor is defined as the integer
portion of a number; PROCCLK is the compute clock; f S AMP
= the FIR input sample rate; R = Decimation Factor; SYM =
1 for symmetrical filter, 0 for asymmetrical filter; ODD# = 1
C Q
C Q(N-1)
for an odd number of filter taps, 0 = an even number of taps.
Use Equation 12A to calculate the maximum input rate.
C Q(0)
COEFFICIENT
NUMBER
C I(N-1)
IENT VA
C I
F SAMP = ( PROCCLK ) ( R ) ? [ R + [ floor [ ( Taps ) +
( SYM ) ( ODD# ) ] ? ( 1 + SYM ) ] ]
(EQ. 12A)
RE AL C
C I(0)
OEFFIC
L UE
for real filters, and
F SAMP = [ ( PROCCLK ) ( R ) ] ? [ R + floor [ ( Taps ) ( 2 ) ] ] (EQ. 12B)
for complex filters, where floor[x], PROCCLK, f S AMP , R =
Decimation Factor, SYM, and ODD# are defined as in
Equation 11A.
COMPLEX FILTERS
Definitions:
Even Symmetric: h(n) = h(N-n-1) for n = 0 to N-1
Odd Symmetric: h(n) = -h(N-n-1) for n = 0 to N-1
Asymmetric: A filter with no coefficient symmetry.
Even Tap filter: A filter where N is an even number.
Use Equation 13 to calculate the maximum output sample
rate for both real and complex filters.
Odd Tap filter:
Real Filter:
A filter where N is an odd number.
A filter implemented with real coefficients.
F FIR OUT = ( F SAMP ) ? R
(EQ. 13)
Complex Filters: A filter with quadrature coefficients.
FIGURE 20. DEMONSTRATION OF DIFFERENT TYPES OF
The coefficients are 22-bits and are loaded using writes to
Control Words 128 through 255 (see Microprocessor Write
Section). For real filters, the same coefficients are used by I
and Q paths. If the filter is configured as a symmetric filter
using Control Word 17, Bit 9, then coefficients are loaded
starting with the center coefficient in Control Word 128 and
proceeding to last coefficient in Control Word 128+n. The
filter symmetry type can be set to even or odd symmetric,
and the number of filter coefficients can be even or odd, as
illustrated in Figure 20. Note that complex filters can also be
realized but are only allowed to be asymmetric. Only the
coefficients that are used need to be loaded.
20
DIGITAL FIR FILTERS CONFIGURED IN THE
PROGRAMMABLE DOWNCONVERTER
Automatic Gain Control (AGC)
The AGC Section provides gain to small signals, after the
large signals and out-of-band noise have been filtered out, to
ensure that small signals have sufficient bit resolution in the
Resampling/Interpolating Halfband filters and the Output
Formatter. The AGC can also be used to manually set the
gain. The AGC optimizes the bit resolution for a variety of
input amplitude signal levels. The AGC loop automatically
adds gain to bring small signals from the lower bits of the 26-
bit programmable FIR filter output into the 16-bit range of the
FN4450.4
May 1, 2007
相关PDF资料 |
PDF描述 |
|---|---|
| HMR2300-D21-232 | MAGNETOMETER RS232 W/CASE |
| V-16-4A5 | SWITCH MINI SPDT 16A PIN PLUNGER |
| HMR2300-D20-232 | MAGNETOMETER RS232 W/CASE |
| D2MV-1L-1C2 | BASIC SWITCH |
| HMR2300-D00-232 | MAGNETOMETER RS232 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214BVI | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214BVIZ | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
发布紧急采购，3分钟左右您将得到回复。