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参数资料
| 型号： | HSP50214BVCZ |
| 厂商： | Intersil |
| 文件页数： | 24/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
range for the AGC rate is ~ 0.000106 to 3.275dB/output
sample time for a threshold of 1/2 scale. See the notes at the
bottom of Table 9A for calculation of the AGC response
times. The maximum AGC Response is given by:
AGC Response Max = Input(Cart/Polar Gain)(Error Det Gain) ( AGC
Loop Gain)(AGC Output Weighting)
(EQ. 19)
Since the AGC error is scaled to adjust the gain, the loop
settles asymptotically to its final value. The loop settles to
the mean of the signal.
TABLE 7. AGC LOOP GAIN BINARY MANTISSA TO GAIN
SCALE FACTOR MAPPING
when AGCGNSEL = 0, and selecting Gain 1 when
AGCGNSEL = 1.
In the HSP50214, a reset event (caused by SYNCIN2 or
CW25) would clear the AGC loop filter accumulator. In the
HSP50214B, if Control Word 27, Bit 15 is set to zero, the
AGC loop filter accumulator will clear as in the original
HSP50214. If Control Word 27, Bit 15 is set to a one, the
backend reset (from CW25) will not clear the AGC loop filter
accumulator.
In the HSP50214, the settling mode of the AGC forces the
mean of the signal magnitude error to zero. The gain error is
scaled and used to adjust the gain up or down. This
proportional scaling mode causes the AGC to settle to the
BINARY
CODE
(MMMM)
0000
0001
0010
0011
0100
0101
0110
0111
SCALE
FACTOR
0.0000
0.0625
0.1250
0.1875
0.2500
0.3125
0.3750
0.4375
BINARY
CODE
(MMMM)
1000
1001
1010
1011
1100
1101
1110
1111
SCALE
FACTOR
0.5000
0.5625
0.6250
0.6875
0.7500
0.8125
0.8750
0.9375
final gain value asymptotically. This AGC settling mode is
preferred in many applications because the loop gain
adjustments get smaller and smaller as the loop settles,
reducing any AM distortion caused by the AGC.
With this AGC settling mode, the proportional gain error
causes the loop to settle more slowly if the threshold is
small. This is because the maximum value of the threshold
minus the magnitude is smaller. Also, the settling can be
asymmetric, where the loop may settle faster for “over
range” signals than for “under range” signals (or vice versa).
In some applications, such as burst signals or TDMA signals,
a very fast settling time and/or a more predictable settling
time is desired. The AGC may be turned off or slowed down
after an initial AGC settling period.
TABLE 8. AGC LOOP GAIN BINARY EXPONENT TO GAIN
SCALE FACTOR MAPPING
To minimize the settling time, a median AGC settling mode
has been added to the HSP50214B. This mode uses a fixed
BINARY
BINARY
gain adjustment with only the direction of the adjustment
CODE
(EEEE)
0000
0001
0010
0011
0100
0101
0110
0111
SCALE
FACTOR
2 15
2 14
2 13
2 12
2 11
2 10-
2 9
2 8
CODE
(EEEE)
1000
1001
1010
1011
1100
1101
1110
1111
SCALE
FACTOR
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
controlled by the gain error. This makes the settling time
independent of the signal level.
For example, if the loop is set to adjust 0.5dB per output
sample, the loop gain can slew up or down by 16dB in 16
symbol times, assuming a 2 samples per symbol output
sample rate. This is called a median settling mode because
the loop settles to where there is an equal number of
magnitude samples above and below the threshold. The
disadvantage of this mode is that the loop will have a wander
(dither) equal to the programmed step size. For this reason,
it is advisable to set one loop gain for fast settling at the
beginning of the burst and the second loop gain for small
adjustments during tracking.
For example, if M LG = 0101 and E LG = 1100, the AGC Loop
Gain = 0.3125*2 -7 . The loop gain mantissas and exponents
are set in the AGC Loop Parameter Control Register (Control
Word 8, Bits 0-15).
Two AGC loop gains are provided in the Programmable Down
Converter, for quick adjustment of the AGC loop. The AGC
Gain select is a control input to the device, selecting Gain 0
24
The median settling mode is enabled by setting Control
Word 27, Bit 16 to a logic one. If Control Word 27, Bit 16 is
zero, the mean loop settling mode is selected and the loop
works identically to the HSP50214.
In the median mode, the loop works as follows:
The sign of the true gain error selects a fixed gain error of
0010000000000 b or 1110000000000 b .
FN4450.4
May 1, 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214BVI | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214BVIZ | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
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