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| 型号： | HSP50214BVCZ |
| 厂商： | Intersil |
| 文件页数： | 7/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
Functional Description
The HSP50214B Programmable Downconverter (PDC) is an
agile digital tuner designed to meet the requirements of a
wide variety of communications industry standards. The
PDC contains the processing functions needed to convert
sampled IF signals to baseband digital samples. These
functions include LO generation/mixing, decimation filtering,
programmable FIR shaping/bandlimiting filtering,
resampling, Automatic Gain Control (AGC), frequency
discrimination and detection as well as multi-chip
synchronization. The HSP50214B interfaces directly with a
DSP microprocessor to pass baseband and status data.
A top level functional block diagram of the HSP50214B is
shown in Figure 1. The diagram shows the major blocks and
multiplexers used to reconfigure the data path for various
architectures. The HSP50214B can be broken into 13
for frequency division multiple access (FDMA) signals. This
high selectivity is achieved with 0.012Hz resolution frequency
control of the NCO and the sharp filter responses capable with
a 255-tap, 22-bit coefficient FIR filter. The 16-bit resolution out
of the Cartesian to Polar Coordinate Converter are routed to
the frequency detector, which is followed by a 63-tap, 22-bit
coefficient FIR filter structure for facilitating FM and FSK
detection. The 14-bit input resolution is the smallest bit
resolution found throughout the conversion and filtering
sections, providing excellent dynamic range in the DSP
processing. A unique input gain scaler adds an additional
42dB of range to the input level variation, to compensate for
changes in the analog RF front end receive equipment.
Synchronization circuitry allows precise timing control of the
base station reconfiguration for all receive channels
simultaneously. Portions of this table were corroborated with
reference [2].
sections: Synchronization, Input, Input Level Detector,
Carrier Mixer/Numerically Control Oscillator (NCO), CIC
Decimating Filter, Halfband Decimating Filter, 255-Tap
Programmable FIR Filter, Automatic Gain Control (AGC),
Re-sampler/Halfband Filter, Timing NCO, Cartesian to Polar
Converter, Discriminator, and Output Sections. All of these
sections are configured through a microprocessor interface.
TABLE 1. CELLULAR PHONE BASE STATION
APPLICATIONS USING FDMA
AMPS MCS-L1 NMT-400
STANDARD (IS-91) MCS-L2 NMT-900 C450
RX BAND 824-849 925-940 453-458 451-456
(MHz) 890-915
CHANNEL 30 25.0 25 20.0
ETACS
NTACS
871-904
915-925
25.0
The HSP50214B has three clock inputs; two are required and
BW (kHz)
12.5
12.5
10.0
12.5
one is optional. The input level detector, carrier NCO, and CIC
decimating filter sections operate on the rising edge of the
input clock, CLKIN. The halfband filter, programmable FIR
# TRAFFIC
CHANNELS
VOICE
832
FM
600
1200
FM
200
1999
FM
222
444
FM
1240
800
FM
filter, AGC, Re-Sampler / Halfband filters, timing NCO,
discriminator, and output sections operate on the rising edge
MODULA-
TION
of PROCCLK. The third clock, REFCLK, is used to generate
PEAK
12
5
5
4
9.5
timing error information.
DEVIATION
(kHz)
NOTE: All of the clocks may be asynchronous.
CONTROL
FSK
FSK
FSK
FSK
FSK
PDC Applications Overview
MODULA-
TION
This section highlights the motivation behind the key
PEAK
8
4.5
3.5
2.5
6.4
programmable features from a communications system level
perspective. These motivations will be defined in terms of ability
DEVIATION
(kHz)
to provide DSP processing capability for specific modulation
CONTROL
10
0.3
1.2
5.3
8
formats and communication applications. The versatility of the
Programmable Downconverter can be intimidating because of
the many Control Words required for chip configuration. This
section provides system level insight to help allay reservations
about this versatile DSP product. It should help the designer
capitalize on the greatest feature of the PDC - VERSATILITY
THROUGH PROGRAMMABILITY . It is this feature, when fully
understood, that brings the greatest return on design
investment by offering a single receiver design that can process
the many waveforms required in the communications
marketplace.
FDM Based Standards and Applications
Table 1 provides an overview of some common frequency
division multiplex (FDM) base station applications to which the
PDC can be applied. The PDC provides excellent selectivity
7
CHANNEL
RATE
(Kbps)
TDM Based Standards and Applications
Table 2 provides an overview of some common Time Division
Multiplexed (TDM) base station applications to which the PDC
can be applied. For time division multiple access (TDMA)
applications, such as North American TDMA (IS136), where
30kHz is the received band of interest for the PCS
basestation, the PDC offers 0.012Hz frequency resolution in
downconversion in addition to α = 0.35 matched
(programmable) filtering capability. The π /4 DPSK modulation
can be processed using the PDC Cartesian to Polar
coordinate converter and d φ /dt detector circuitry or by
processing the I/Q samples in the DSP μ P. The PDC provides
FN4450.4
May 1, 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214BVI | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214BVIZ | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
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