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参数资料
| 型号： | HSP50214BVCZ |
| 厂商： | Intersil |
| 文件页数： | 32/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
The Discriminator FIR filter input selections are made in
Control Word 27, Bits 18 and 19. The bit definitions are:
00 Item (1) described above.
01 Item (2) described above.
1X Item (3) described above.
Control Word 27, Bit 14 is used to control the Q input to the
coordinate converter. The bit definitions is:
request strobes from the controller ensures that data is
transferred only when both the controller and the
Programmable Down Converter are ready. The Buffer RAM
output can be operated in a First In First Out (FIFO) or
SNAPSHOT mode with the data output either via the 8-bit
processor interface or a 16-bit processor interface.
Parallel Direct Output Port Mode
The Parallel Direct Output Port Mode outputs two 16-bit words,
0
1
I and Q enabled to the I/Q to R/Theta block.
The Q input to the I/Q to R/Theta block is zeroed.
AOUT and BOUT, of “real time” data. Figure 30 details the
parallel output circuitry. Selection of the data source for the
AOUT and BOUT parallel outputs is done via Control Word 20,
The enable signals associated with the various input
selections to the Discriminator FIR filter are:
Bits 22-23, and 20-21, respectively. The AOUT port can output
I, Magnitude, or Frequency data. The BOUT port can output Q,
1
2
The data ready strobe from the coordinate con-
verter block.
The data ready strobe from the coordinate con-
verter block.
Phase or Magnitude data. The upper bytes of AOUT and
BOUT are always in the parallel direct mode. The 16-bit parallel
direct mode is selected by setting Control Word 20, Bit 25, to
zero.
The enable signals associated with the various input
selections to the coordinate converter are:
The DATARDY output is asserted during the first clock cycle
of the new data on the AOUT bus. The rate at which the data
3a
3b
The data ready signal to the coordinate converter
block when the resampler is bypassed. This is the
AGC output data ready signal.
The data ready to the coordinate converter block
out of the HSP50214 transitions and the rate at which
DATARDY is asserted can be different.
Data Transitions:
The transition rate of the parallel output data is dependent on
when the resampler/halfband filters are enabled.
This is the resampler halfband filter block output
data ready signal.
The discriminator input is 18-bits, and the output is rounded
asymmetrically to 16-bits. The phase into the discriminator
can be multiplied by 2 0 , 2 1 , 2 2 , or 2 3 (modulo 2 π ) to remove
PSK data modulation. All programmable parameters for the
Frequency Discriminator are set in Control Word 17. Bits 15
and 16 are the phase multiplier which represents the shift
applied to the input phase. For CW, the multiply should equal
which of the three types of data is selected for the AOUT
Output channel: I (real symbols), |r| (magnitude), or f
(frequency). Q (quadrature symbols), ? (phase), or |r|
(magnitude) are available on the BOUT output. When selected
as an output, the I Q, |r|, and ? outputs transition at the symbol
rate. The f (frequency) output transitions at the discriminator
FIR filter output rate.
AOUT DIRECT PAR
OUTPUT MODE
DATA SOURCE ?
2 0 , (00). For BPSK, QPSK, and 8PSK, the multiply should
equal 2 1 , (01); 2 2 , (10); or 2 3 , (11); respectively. Bit 14 is
used to enable or disable the discriminator. Bits 11-13 set the
decimation in the programmable FIR filter. Bit 10 sets the
filter symmetry type as either odd or even, bit 9 sets whether
I
(2’s COMPLEMENT)
MAG
(UNSIGNED BINARY)
FREQ
16
16
16
A(15:8)
A(7:0)
RAM(15:8)
DATARDY
AOUT(15:8)
AOUT(7:0)
the filter is asymmetric or symmetric, and bits 3-8 set the
number of FIR filter taps. Bits 0-2 set the number of delays in
the frequency discriminator.
Output Section
(2’s COMPLEMENT)
BOUT DIRECT PAR
OUTPUT MODE
DATA SOURCE ?
The Output Section routes the 7 types of processed signals to
output pins in three basic modes. These basic modes are:
Parallel Direct Output, Serial Direct Output, and the Buffer
RAM Output. The Serial and Parallel Direct Output modes
were designed to output data strobes and “real time”
Q
(2’s COMPLEMENT)
PHAS
(2’s COMPLEMENT)
MAG
(UNSIGNED BINARY)
16
16
16
B(15:8)
B(7:0)
RAM (7:0)
BOUT(15:8)
BOUT(7:0)
continuous streams of data. The Buffer RAM Output mode
outputs data upon receipt of an asynchronous request from an
external DSP processor or other baseband processing
engine. The use of the interrupt signal from the
Programmable Down Converter in conjunction with the
32
RAM (15:0)
DATA SOURCE FOR LSB ?
? Controlled via microprocessor interface.
FIGURE 30. PARALLEL OUTPUT BLOCK DIAGRAM
FN4450.4
May 1, 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214BVI | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214BVIZ | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
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