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参数资料
| 型号： | HSP50214BVCZ |
| 厂商： | Intersil |
| 文件页数： | 43/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE
PROCLK
STEP
A(2:0)
C(7:0)
COMMENT
1
000
0011 1000 Loads 38 into Master Register
(7:0) on rising edge of WR.
WR
RD
2
3
001
010
1101 0000 Loads D0 into Master Register
(15:8) on rising edge of WR.
0001 1000 Loads 18 into Master Register
A2-0
C7-0
5
READ ADDRESS
OUTPUT DATA C(7:0)
(23:16) on rising edge of WR.
READ CODE C(2:0)
4
011
0000 0000 Loads 00 into Master Register
(31:24) on rising edge of WR.
LOAD ADDRESS
OF TARGET
CONTROL REGISTER
THREE-STATE
INPUT BUS
ASSERT RD
TO ENABLE DATA
OUTPUT ON C0-7
5
100
0000 0000 Load “0018D038” into
Configuration Control Register 0.
FIGURE 46. READING THE CONTROL REGISTERS USING A
LATCH CODE EQUAL TO A 5, A READ ADDRESS
AND A READ CODE
6
Wait 4 CLKS.
TABLE 21. PROCESSOR READ SEQUENCE (INPUT LEVEL
SELECTOR)
CLK =
(PROCCLK,
1
2
3
4
STEP
A(2:0)
C(7:0)
COMMENT
CLKIN)
WR
1
101
100
Write Read Code, 100 to
Address 5, WR pulled high to
generate rising edge.
A2-0
0
1
2
3
4
0
2
C7-0
LSB
MSB ADD
2
000
1111 1000
(F4)H
Drop RD low, Read AGC LSB.
LOAD
CONFIGURATION
DATA
LOAD ADDRESS OF
TARGET CONTROL
REGISTER AND
WAIT 4 CLKs
LOAD NEXT
CONFIG-
URATION
REGISTER
3
4
001
010
0001 1010 Pull RD high, then drop low,
(1A)H Read AGC NLSB.
0011 0010 Pull RD high, then drop low,
(32)H Read AGC MSB.
FIGURE 45. LOADING THE CONTROL REGISTERS WITH
32-BIT CONTROL WORDS
TABLE 22. DEFINITION OF ADDRESS MAP
Microprocessor Read Section
READ
CODE C(2:0)
STATUS
TYPE
READ ADDRESS A(2:0)
The microprocessor read uses both read and write
procedures to obtain data from the PDC. A write must be
done to location 5 to select the source of data to be read.
The read source is determined by the value placed on the
lower three bits of C(7:0). The output from a particular read
code is selected using a read address placed on A(2:0). The
output is sent to C(7:0) on the falling edge of RD.
000
001
Buffer RAM 000- I LSB.
I and Q 001- I MSB.
010- Q LSB.
011- Q MSB.
See Output Section.
Buffer RAM 000- MAG LSB (7-0).
Output 001- MAG MSB (15-8).
If the Read Address is equal to 111, the Read Code is
ignored, and the status bits shown in Table 22 in the Output
Section is sent to C(7:0). This state was provided so that the
(|r| and φ)
010- PHASE LSB (7-0).
011- PHASE MSB (15-8).
See Output Section.
user could obtain the status bits quickly.
Refer to the Timing Diagram in Figure 46. Suppose the input
level detector has a hex value of (321AF5)H, then Table 21
details the steps to be taken.
43
010
011
100
Buffered 000- FREQ LSB.
Frequency 001- FREQ MSB.
See Output Section.
Not Used
Input Level Input AGC
Detector
000- input AGC LSB (0-7).
001- input AGC NLSB (8-15).
010- input AGC MSB (16-23).
FN4450.4
May 1, 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214BVI | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214BVIZ | 功能描述:上下转换器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
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