参数资料
型号: HSP50214BVCZ
厂商: Intersil
文件页数: 38/62页
文件大小: 0K
描述: IC DOWNCONVERTER 14BIT 120-MQFP
标准包装: 24
功能: 降频器
RF 型: AMPS,CDMA,GSM,TDMA
封装/外壳: 120-BQFP
包装: 托盘
HSP50214B
The FIFO mode allows the processor to service the interface
only when enough samples are present in the RAM. This
mode is provided so that the μ Processor does not have to
service the PDC every output sample. An interrupt,
INTRRPT, is asserted when the desired number of samples
I
Q
|r|
φ
?
16
16
16
16
16
DUAL
PORT
RAM
I       0
Q      1
|r|      2
φ 3
? 4
STATUS 6
OUTPUT
DATA
are available. The PDC can be programmed to assert the
interrupt when up to 7 samples are available. Control Word
21, Bit 15 is used to set the Buffer RAM controller to the
FIFO mode, while Control Word 21, Bits 12-14 set the
number of RAM samples to be stored (0 to 7) before the
interrupt (INTRRPT) is asserted. Control Word 20, Bit 24
determines whether the RAM output interface is the 8-bit
WRITE
SEQUENCER
NEW
DATA
“SET OF WORDS”
ADDRESS
SEQUENCER
INCR INCR
RD
WR
PROCCLK
OEBL
SEL(2:0)
microprocessor interface or the 16-bit processor interface. In
the 16-bit interface the MSByte is sent to AOUT(7:0) while
the LSByte is sent to BOUT(7:0).
The INTRRP output signal goes low for 8 PROCCLK cycles
FIGURE 37. 16-BIT MICROPROCESSOR INTERFACE BUFFER
RAM MODE BLOCK DIAGRAM
TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS
when the number of samples in the Buffer RAM (depth)
reaches the programmed depth. The depth of the RAM is
calculated using Equation 23. A DSP microprocessor or the
data processing engine can use the INTRRP signal to know
that the RAM is ready to be read.
SEL(2:0)
000
001
010
I Data
Q Data
Magnitude
OUTPUT DATA TYPE
D RAM = [ ( ADDR WRITE – ADDR READ ) – 1 ] MOD8
(EQ. 23)
011
100
Phase
Frequency
FIFO Operation Via 16-Bit μ Processor
Interface
Figure 37 shows the conceptual configuration of the 16-bit
μ Processor interface. This interface looks like a 16-bit
μ Processor read-only microprocessor interface. The
SEL(2:0) lines are the address bus and the OEAL and OEBL
101
110
111
Unused
Memory Status
Reading this address increments to the next
sample set
lines are the read lines. The address is decoded as shown in
Table 17.
TABLE 18. STATUS BIT DEFINITIONS
AOUT BIT
Use of the 16-bit interface for Buffer RAM output requires
Control Word 20, Bit 25, to be set to a logic “0” and Control
Word 20, Bit 24, to be set to a logic “1”. Once the Control
Word 20 has been set to route data to AOUT(7:0) and
BOUT(7:0), then the microprocessor must place a value on
the PDC input pins SEL(2:0), to choose which data type will
be output on AOUT(7:0) and 6BOUT(7:0). Table 17 defines
the data types in terms of SEL(2:0). With the control lines
set, the selected data is read MSByte on AOUT(7:0) and
LSByte on BOUT(7:0) when OEAL and OEBL (are low).
New data only read when OEBL goes low, so use μ P for 8-
bit modes. Programming SEL(2:0) = 110 outputs a 16-bit
status signal on AOUT and BOUT. The FIFO status includes
FULL, EMPTY, FIFO Depth, and READYB. These status
LOCATION
(7:5)
4
3
2
1-0
INFORMATION
FIFO depth - When in FIFO mode, these bits are
the current depth of the FIFO.
EMPTY - When in FIFO mode, the FIFO is
empty, and the read pointer cannot be
advanced. Active High.
FULL - When in FIFO mode, the FIFO is full, and
new samples will not be written.
Active High.
READYB - When in FIFO mode, the output
buffer has reached the programmed threshold.
In the snapshot mode, the programmed number
of samples have been taken. Active Low.
GND
signals are defined in Table 18.
38
NOTE: In the Status output, BOUT(7:0) are all GND.
FN4450.4
May 1, 2007
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