收藏本站
参数资料
型号： HSP50214BVIZ
厂商： Intersil
文件页数： 12/62页
文件大小： 0K
描述： IC DOWNCONVERTER 14BIT 120-MQFP
标准包装： 24
功能： 降频器
RF 型： AMPS，CDMA，GSM，TDMA
封装/外壳： 120-BQFP
包装： 托盘
HSP50214B
ACCUMULATOR
32
ADDR(2:0)
IN(13:0)
INPUT
GATING
LOGIC
|X|
+
+
CLKIN
R
E
G
R
E
G
24
M
U
X
8
TO
μ PROC
INPUT_THRESHOLD ?
R
E
G
INTEGRATION_INTERVAL ?
START ?
16
“0”
INTEGRATION_MODE ?
CLKIN
COUNTER
? Controlled via microprocessor interface.
CONTINUOUS
SINGLE
FIGURE 9.
The integration period counter can be set up to run
continuously or to count down and stop. Continuous integration
counter operation lets the counter run, with sampling occurring
every time the counter reaches zero. Because the processor
samples the detector read port asynchronous to the CLKIN,
data can be missed unless the status bit is monitored by the
S 2
f 0
-6dB 2 -1
-12dB 2 -2
-18dB 2 -3
-24dB 2 -4
-30dB 2 -5
-36dB 2 -6
-42dB 2 -7
-48dB 2 -8
-54dB 2 -9
-60dB 2 -10
-66dB 2 -11
-72dB 2 -12
-78dB 2 -13
2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
2 -8
2 -9
2 -10
2 -11
2 -12
2 -13
0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
2 -8
2 -9
2 -10
2 -11
2 -12
2 -13
-2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
2 -8
2 -9
2 -10
2 -11
2 -12
2 -13
2 18
2 17
2 16
2 15
2 14
2 13
2 12
2 11
2 10
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
2 -8
2 -9
2 -10
2 -11
2 -12
2 -13
0
2 18
2 17
2 16
2 15
2 14
2 13
2 12
2 11
2 10
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
2 -1
2 -2
2 -3
2 -4
processor to ensure that a sample is taken for every integration
count down sequence.
Additionally, in the HSP50214B, the ability to align the
start/restart of the input level detector integration period with
an external event is provided. This allows the sync signals,
which are synchronized to external events, to be used to align
all of the gain adjustments or measurements. If Control Word
27, Bit 17 is set to a logic one, the SYNCIN1 signal will cause
the input level detector to start/restart its integration period. If
Control Word 27, Bit 17 is set to a logic zero, control of the
start/restart of the input level detector integration period does
not respond to SYNCIN1.
In the count down and stop mode, the microprocessor read
commands can be synchronized to system events, such as the
start of a burst for a TDMA application. The integration counter
can be started at any time by writing to Control Word 2. At the
end of the integration period (counter = 0000), the upper 23-bits
of the accumulator are transferred to a holding register for
reading by the microprocessor. Note that it is not the restarting
of the counter (by writing to Control Word 2) that latches the
current value, but the end of the integration count. When the
accumulator results are latched, a bit is set in the Status
Register to notify the processor. Reading the most significant
byte of the 23-bits clears the status bit. See the Microprocessor
Read Section. Figure 11 illustrates a typical AGC detection
FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING
12
process.
FN4450.4
May 1, 2007
相关PDF资料
PDF描述
HSP50216KIZ IC DOWNCONVERTER DGTL 4CH 196BGA
HSP50415VIZ IC MODULATOR PROGRAMABLE 100MQFP
HSSLS-CALBL-013 HEATSINK 48W SPOT OSRAM PREVALED
HSSLS-CALCL-005 HEATSINK 21W SPOT PHILIPS SLM
HSSLS-CALCL-013 HEATSINK 48W DOWNLIGHT 140
相关代理商/技术参数
参数描述
HSP50214VC 制造商:Rochester Electronics LLC 功能描述:- Bulk
HSP50214VI 制造商:Rochester Electronics LLC 功能描述:- Bulk
HSP50215 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board
HSP50215EVAL 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board
HSP50215VC 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital UpConverter
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*