参数资料
型号: HSP50214BVIZ
厂商: Intersil
文件页数: 40/62页
文件大小: 0K
描述: IC DOWNCONVERTER 14BIT 120-MQFP
标准包装: 24
功能: 降频器
RF 型: AMPS,CDMA,GSM,TDMA
封装/外壳: 120-BQFP
包装: 托盘
HSP50214B
FIFO Operation Via 8-Bit μ Processor
Interface
The Buffer RAM Output may also be accessed via the 8-bit
6
7
microprocessor interface C(7:0). Figure 41 shows the
conceptual configuration of the 8-bit μ processor interface.
5
4
3
2
0
1
FIFO
DEPTH
WRITE
Control Word 20, Bit 24 must be set to 0 in order to obtain
Buffer RAM data to this output. The Microprocessor Read
Section describes how to read the data from each sample
out of the C(7:0) interface.
Recall that INTRRP stays low for 8 PROCCLK cycles. The
FIFO can be read before the INTRRP signal goes low; the
FIGURE 40A. FIFO DEPTH IS (WRITE - READ )
WRITE
number of samples in the FIFO must be monitored by the user.
The timing relationship of the INTRRP to the snapshot data is
shown in Figure 42.
The read pointer of the FIFO is incremented when Control
Word 23 is written to. The data cannot be read from the
next sample until 4 PROCCLKs after the Buffer RAM
5
4
6
3
7
2
0
1
READ
pointer has been incremented. Control Word 22 is used to
reset the Read and Write pointers of the Buffer RAM output
to the first sample to 000 and 007 for write and read
respectively.
FIGURE 40B. FIFO FULL IS WHEN (WRITE - READ) = 7
READ
5
4
6
3
7
2
0
1
WRITE
FIGURE 40C. FIFO EMPTY IS WHEN (WRITE - READ) = 1
READ
5
4
6
7
0
1
WRITE
3
2
READY
FIGURE 40D. FIFO READY IS WHEN (WRITE - READ) > DEPTH
FIGURE 40.
40
FN4450.4
May 1, 2007
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