参数资料
型号: HSP50214BVIZ
厂商: Intersil
文件页数: 54/62页
文件大小: 0K
描述: IC DOWNCONVERTER 14BIT 120-MQFP
标准包装: 24
功能: 降频器
RF 型: AMPS,CDMA,GSM,TDMA
封装/外壳: 120-BQFP
包装: 托盘
HSP50214B
CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION
(SYNCHRONIZED WITH PROCCLK) (Continued)
BIT
POSITION
11-10
FUNCTION
Q Data Serial Output
Tag Bit
DESCRIPTION
(See I Data Serial Output Tag selection above).
9-8
Magnitude Data Serial (See I Data Serial Output Tag selection above).
Output Tag Bit
7-6
Phase Data Serial
Output Tag Bit
(See I Data Serial Output Tag selection above).
5-4
Frequency Data Serial (See I Data Serial Output Tag selection above).
Output Tag Bit
3-2
1-0
AGC Data Serial
Output Tag Bit
Timing Error Data
(See I Data Serial Output Tag selection above).
(See I Data Serial Output Tag selection above).
Serial Output Tag Bit
CONTROL WORD 21: BUFFER RAM OUTPUT CONTROL REGISTER (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-16
15
14-12
11-4
3-0
FUNCTION
Reserved
Output Buffer Mode
FIFO Mode Depth
Threshold
Snapshot Mode
Interval
Snapshot Mode
Number of Samples
DESCRIPTION
Reserved.
0- The output buffer operates in snapshot mode.
1- The output buffer operates in FIFO mode.
In FIFO mode, when the FIFO depth reaches this threshold, an interrupt is generated and the READY
flag is asserted. The threshold may be set from 0 to 7. Bit 14 is the MSB. The interrupt is generated when
the FIFO depth reaches the threshold, as the FIFO fills.
In snapshot mode, the interval between snapshots in the output sample times is determined by this 8-
bit binary number, i.e. 256, (2 8 ), sample time counts between snapshot samples. Program this
parameter to 1 less than the desired interval. Bit 11 is the MSB.
In snapshot mode, the number of samples stored each time the snapshot interval counter times out is
equal to the decimal version of this 4-bit number. The range is 1- 8. Bit 3 is the MSB.
CONTROL WORD 22: BUFFER RAM OUTPUT FIFO RESET (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
N/A
FUNCTION
FIFO reset
DESCRIPTION
A write to this address increments the output FIFO RAM address pointers to READ = 111 and WRITE =
000.
CONTROL WORD 23: INCREMENT OUTPUT FIFO (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
N/A
FUNCTION
FIFO Strobe
DESCRIPTION
A write to this address increments the output FIFO/buffer to the next sample set.
CONTROL WORD 24: SYNCOUT STROBE OUTPUT PIN
(SYNCHRONIZED TO CLKIN OR PROCCLK DEPENDING ON PROGRAMMING IN CONTROL WORD 0)
BIT
POSITION
N/A
FUNCTION
SYNCOUT Strobe
54
DESCRIPTION
A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is
synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the
programming of bit 3 of Control Word 0.
FN4450.4
May 1, 2007
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