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参数资料
| 型号： | HSP50214BVIZ |
| 厂商： | Intersil |
| 文件页数： | 41/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
I
Q
|r|
φ
?
16
16
16
16
16
DUAL
PORT
RAM
I
Q
|r|
φ
?
0
1
2
3
4
0
LSByte
0
R2 R1 R0 A2 A1 A0 SELECTION
0 0 0 0 0 0 RAM I LSB
0 0 0 0 0 1 RAM I MSB
0
0
0
0
1
0 RAM Q LSB
1
WRITE
SEQUENCER
NEW
“SET OF WORDS”
ADDRESS
SEQUENCER
INCR INCR
WR RD
R1 R0 A1
STATUS
1
R2
MSByte
A0
0
1
OUTPUT
DATA
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1 RAM Q MSB
0 RAM |r| LSB
1 RAM |r| MSB
0 RAM φ LSB
1 RAM φ MSB
0 RAM ? LSB
DATA
0
1
0
0
0
1 RAM ? MSB
R2, R1, R0
ADDRESS “5”
CONTROL
WORD 23
A(2:0)
INT(15:0)
WRITE
INT(22:16)
A2, A1, A0 AGC
0: I;Q (2’s COMP) TIMING
1: |r|; φ (O; UNSIGNED BINARY; 2’s COMP)
2: ? (2’s COMPLEMENT)
0
1
2
3
R0 A1
A2 A1 A0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
X
0
0
0
0
0
0
X
0
0
1
0
0
1
X NOT USED
0 INPUT INTEG LSB
1 INPUT INTEG NMSB
0 INPUT INTEG MSB
0 AGC LSB
1 AGC MSB
0 TIMING LSB
4: INPUT AGC (O; UNSIGNED BINARY)
5: AGC; TIMING (O; UNSIGNED BINARY;
2’s COMP)
1
1
X
0
1
X
1
X
X
0
X
1
1
X
1
1 TIMING MSB
X NOT USED
1 STATUS
RD
FIGURE 41. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM
PROCCLK
DATARDY
(I/Q SELECTED)
DATARDY
(R/ φ SELECTED)
INTRRP
I/Q
R/ φ
DELAY TO DATARDY DEPENDS ON LENGTH OF FIR IF FREQ CHOSEN
WRITES TO
SNAPSHOT
I
Q
R
φ
?
RAM
FIGURE 42. RAM LOAD SEQUENCE
Snap Shot Operation
The snapshot mode takes sets of adjacent samples at
programmed intervals. It is provided for tracking algorithms
that do not require processing of every sample, but do
require sets of adjacent samples. For example, bit sync
algorithms have narrow loop bandwidths that may not need
to be updated every sample. Computing the bit phase may
require 4 adjacent samples at 2 times the baud rate. The
snapshot mode allows the processor to implement the
tracking algorithms for high speed data without having to
value programmed plus 1. If bits 11-4 = 11111111, then the
interval is set to 256. If sample sets are to be taken every 4
samples, then bits 11-4 = 00000011.
Figure 43 shows the relationship between the snapshot
samples and the snapshot interval.
ADJACENT
SAMPLES
handle every data sample.
0
1
2
3
4
62
63
64
65
The interval from the start of one snapshot to the start of a
second snapshot is programmed into bits 11-4 (where bit 11
is the MSB) of Control Word 21. The actual interval is the
41
# SAMPLES = 4
INTERVAL = 64
FIGURE 43. SNAP SHOT SAMPLING
FN4450.4
May 1, 2007
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|---|---|
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| HSP50415VIZ | IC MODULATOR PROGRAMABLE 100MQFP |
| HSSLS-CALBL-013 | HEATSINK 48W SPOT OSRAM PREVALED |
| HSSLS-CALCL-005 | HEATSINK 21W SPOT PHILIPS SLM |
| HSSLS-CALCL-013 | HEATSINK 48W DOWNLIGHT 140 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital UpConverter |
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