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参数资料
型号： HSP50214BVIZ
厂商： Intersil
文件页数： 49/62页
文件大小： 0K
描述： IC DOWNCONVERTER 14BIT 120-MQFP
标准包装： 24
功能： 降频器
RF 型： AMPS，CDMA，GSM，TDMA
封装/外壳： 120-BQFP
包装： 托盘
HSP50214B
CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-22
21
20
19
18
17
16
15
14-11
10
9
8
7-0
FUNCTION
Reserved
Enable External
Filter Sync
Halfband (HB)
Bypass
HB5 Enable
HB4 Enable
HB3 Enable
HB2 Enable
HB1 Enable
FIR Decimation
FIR Real/Complex
FIR Sym Type
FIR Symmetry
FIR Taps
DESCRIPTION
Reserved.
0- The SYNCIN2 pin has no effect on the halfband and FIR filters.
1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR, the
resampler, and the discriminator are reset. SYNCIN2 can be used to synchronize the computations of
the filters in multiple parts for the alignment (see Synchronization Section).
1- Bypass Halfband Filters.
0- Enable HB Filters (at least one HB must be enabled).
0- Disables HB number 5 (the last in the cascade).
1- Enables HB filter number 5.
Setting this bit enables HB filter number 4.
Setting this bit enables HB filter number 3.
Setting this bit enables HB filter number 2.
Setting this bit enables HB filter number 1.
Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB.
0001 - 1 1001 - 9
0010 - 2 1010 - 10
0011 - 3 1011 - 11
0100 - 4 1100 - 12
0101 - 5 1101 - 13
0110 - 6 1110 - 14
0111 - 7 1111 - 15
1000 - 8 0000 - 16
0- Complex Filter.
1- Dual Real Filters.
0- Odd Symmetry.
1- Even Symmetry.
0- Symmetric Filters.
1- Asymmetric Filters.
Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid.
CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-30
29
28-16
15-12
11-8
7-4
3-0
FUNCTION
Reserved
Sync AGC Updates to
SYNCIN2
Threshold
Loop Gain 1
Mantissa
Loop Gain 1
Exponent
Loop Gain 0 Mantissa
Loop Gain 0
Exponent
49
DESCRIPTION
Reserved.
When this bit is 1, the SYNCIN2 pin loads the contents of the master registers into the AGC accumulator.
The magnitude measurement out of the cartesian to polar converter is subtracted from this value to get
the gain error. A gain of 1.647 in the cartesian to polar conversion that must be taken into account when
computing this threshold. These bits are weighted -2 2 down to 2 -10 . Bit 28 is the MSB.
Selected when AGCGNSEL = 1. These bits, MMMM, together with the exponent bits, EEEE (11-8), set
the loop gain for the AGC loop. The gain adjustment per output sample is:
1.5dB (Threshold -[Magnitude * 1.6]) 0.MMMM * 2 -(15 - EEEE) where magnitude ranges from 0 to 1.414
and the threshold is programmed in bits 28-16. The decimal value for the mantissa is calculated as
DEC(MMMM)/16. Bit 15 is the MSB.
Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is the MSB.
Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same equations
are used for Loop 0. Bit 7 is the MSB.
Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same equations
are used for Loop 0. Bit 3 is the MSB.
FN4450.4
May 1, 2007
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