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参数资料
| 型号： | HSP50214BVIZ |
| 厂商： | Intersil |
| 文件页数： | 29/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
EN EXT TIMING NCO SYNC
?
TIMING
SYNCIN2
TIMING PHASE STROBE
SYNC
?
5
FILTER PHASE
SELECT
CARRY OUT = RUN
NCO
ACC.
NCO DIVIDE ?
(NCO DIVIDE)/2 ?
TIMING NCO
PHASE OFFSET ?
PHASE
ACCUMULATOR
8
+
FILTER STROBE
CLEAR
PHASE
0 ACC ?
PROGRAMMABLE
DIVIDER
12
4
-
+
TE(15:0)
REG
MUX
REFERENCE
+
DIVIDE ?
EN
ENABLE SOF ?
SOF
32
MUX
0
32
SCF
REG
SYNC
TIMING NCO
PH ACC
LOAD ON
UPDATE ?
PROGRAMMABLE
REFCLK
DIVIDER
? Controlled via microprocessor interface.
REG
REG
FIGURE 27. TIMING ERROR GENERATION
SOFSYNC
SOF
SYNC
SHIFT REG
TIMING FREQ
STROBE ?
Figure 27A illustrates an application where the Timing Error
Generator is used to lock the receiver samples with a
transmit data rate. In this example, the receive samples are
NUMBER OF SOF BITS
?
TIMING NCO CENTER
FREQUENCY ?
at four times the transmit data rate. An external loop filter is
required, whose frequency error output is fed into the Timing
? Controlled via microprocessor interface.
NCO. This allows the loop to track out the long term drift
between the receive sample rate and the transmit data clock.
FIGURE 26. TIMING NCO BLOCK DIAGRAM
The programmable parameters for the Timing NCO include
an Enable External Timing NCO Sync (Control Word 11, Bit
5), the serial word width, Number of Offset Frequency Bits
(Control Word 11, Bits 3-4), an Enable Offset Frequency
control (Control Word 11, Bit 2), a Clear NCO Accumulator
control (Control Word 11, Bit 1), a Timing NCO Phase
TIMING
NCO
μ P
LOOP
FILTER
Accumulator Load On Update control (Control Word 11, Bit
0), the Timing NCO Center Frequency (Control Word 12), a
Timing Phase Offset (Control Word 13, Bits 0-7), a Timing
Frequency Strobe (Control Word 14) and a Timing Phase
ACC.
CLKIN/R T
NCO DIVIDE = 4N ?
(NCO DIVIDE)/2 ?
-
Strobe (Control Word 15). Refer to the Carrier Synthesizer
Mixer Section for a detailed discussion of the serial interface
PROGRAMMABLE
DIVIDER
12
+
TE(15:0)
for the Timing NCO offset frequency word.
A timing error detector is provided for measuring the phase
REFERENCE
4
difference between the timing NCO and a external clock input,
REFCLK. Timing Error is generated by comparing the values
DIVIDE = N ?
EN
of two programmable counters. One counter is clocked with
the Timing NCO carry out and the other is clocked by the
REFCLK. The 12-bit NCO Divide parameter is set in Control
Tx DATA CLK
(REFCLK)
PROGRAMMABLE
DIVIDER
Word 18, Bits 16-27. The NCO Divide parameter is the
preload to the counter that is clocked by the Timing NCO carry
out. The 12-bit Reference Divide parameter is set in Control
Word 18, Bits 0-11, and is the preload for the counter that is
clocked by the Reference clock. Figure 26 details the block
diagram of the timing error generation circuit. The 16-bits of
timing error are available both as a PDC serial output and as a
processor read parameter. See the Processor Read Section
for more details on accessing this value.
29
TO Tx BLOCK
(MODULATOR)
R T = TOTAL DECIMATION (CIC, HB FILTERS AND FIR)
? Controlled via microprocessor interface.
FIGURE 27A. TIMING ERROR APPLICATION
FN4450.4
May 1, 2007
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相关代理商/技术参数 |
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| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital UpConverter |
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