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参数资料
| 型号： | HSP50214BVIZ |
| 厂商： | Intersil |
| 文件页数： | 50/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-28
27-16
15-12
11-0
FUNCTION
Reserved
Upper Limit
Reserved
Lower Limit
DESCRIPTION
Reserved.
Maximum Gain/Minimum Signal. The upper four bits are used for exponent; the remaining bits form the
mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 27 is
the MSB. The gain is in dB. G = (6.02)(eeee) + 20log 10 (1.0 + 0.mmmmmmmm)
eeee = Floor [log 2 (10 GAIN dB/20 )]
mmmmmmmm = Floor [256(10 GAIN dB/20 /2 eeee - 1)]
Reserved.
Minimum Gain/Maximum Signal. The upper four bits are used for exponent; the remaining bits form the
mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 11 is
the MSB. The gain is in dB. G = (6.02)(eeee) + 20log 10 (1.0 + 0.mmmmmmmm)
eeee = Floor [log 2 (10 GAIN dB/20 )]
mmmmmmmm = Floor [256(10 GAIN dB/20 /2 eeee - 1)]
CONTROL WORD 10: AGC SAMPLE GAIN CONTROL STROBE (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
N/A
FUNCTION
Sample AGC Gain
DESCRIPTION
Writing to this location samples the output of the AGC loop filter to stabilize the value for μ P reading.
Level
CONTROL WORD 11: TIMING NCO CONFIGURATION (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-6
5
4-3
2
1
0
FUNCTION
Reserved
Enable External
Timing NCO Sync
Number of Offset
Frequency Bits
Enable Offset
Frequency
Clear Phase
Accumulator
Timing NCO Phase
Accumulator Load On
Update
DESCRIPTION
Reserved.
0- SYNCIN2 has no effect on the timing NCO.
1- When SYNCIN2 is asserted, the timing NCO center frequency and phase are updated with the value
loaded in their holding registers. If bit 0 of this word is set to 1, the phase accumulator feedback is also
zeroed.
00 - 8 bits.
01 - 16.
10 - 24.
11 - 32.
0- Zero Offset Frequency to Adder.
1- Enable Offset Frequency.
0- Enable Accumulator.
1- Zero Feedback in Accumulator.
When this bit is set to 1, the μ P update to the timing NCO frequency or an external timing NCO load
using SYNCIN2 will zero the feedback of the phase accumulator as well as update the phase and
frequency. This function can be used to set the NCO to a known phase synchronized to an external
event.
CONTROL WORD 12: TIMING NCO CENTER FREQUENCY (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-0
FUNCTION
Timing NCO Center
Frequency
50
DESCRIPTION
These bits control the frequency of the timing NCO. The frequency range of the NCO is from 0 to
F RESAMP where F RESAMP is the input sample rate to the resampling filter. The bits are computed by
the equation: N =(f OUT / F RESAMP )*2 32 . Bit 31 is the MSB. This location is a holding register. After
loading, a transfer to the Active Register is done by writing to Control Word 14 or by generating a
SYNCIN2 with Control Word 11, Bit 5 set to 1.
FN4450.4
May 1, 2007
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相关代理商/技术参数 |
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|---|---|
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital UpConverter |
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