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参数资料
| 型号： | HSP50214BVIZ |
| 厂商： | Intersil |
| 文件页数： | 33/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
Data Ready Signal Assertion Rate:
The assertion rate of the DATARDY signal Is the data
transition rate of the A OUT output data either [I, |r| or f]. The
time alignment of parallel data words available for output are
as follows:
Note that the BOUT data word may be at a different rate and
skewed in time with respect to DATARDY, depending on the
type of data selected for output. This is because of the timing
relationships defined above, and because the DATARDY is
driven by the AOUT signal. Figure 32 details such a
configuration.
? I and Q are aligned in time,
? |r| and ? are time aligned, but one sample clock delayed
from the associated I and Q samples.
DATARDY Is asserted time aligned with and at the same
rate as the data type selected for the AOUT output.
Figure 31 details the timing of the AOUT and DATARDY for
an AOUT = I data selection.
When the f (frequency) word is selected for output on AOUT,
the DATARDY signal is asserted at the discriminator FIR
filter output rate, which will be a reduced rate when
decimation is engaged in the filter. The f (frequency)S output
is delayed from the associated I and Q samples one sample
time plus, the discriminator FIR filter impulse response time.
Figure 33 details the timing of this configuration for a FIR
filter that decimates by 4.
AOUT
I0
I1
I2
I3
I4
I5
I6
PROCCLK
DATARDY
DR0
DR1
DR2
DR3
DR4
DR5
DR6
NOTE: The number of PROCCLKS per output symbol is not representative, but shown to be small for clarity of establishing timing with respect to
the DATARDY signal. For each application, the relationship of the output symbol rate to PROCCLK must be properly illustrated to determine the
exact nature of the timing.
FIGURE 31. DATARDY WAVEFORMS WHEN I (READ DATA) IS SELECTED AS AOUT
BOUT
Q0
Q1
Q2
Q3
Q4
Q5
Q6
AOUT
|r|0
|r|1
|r|2
|r|3
|r|4
|r|5
|r|6
PROCCLK
DATARDY
DR0
DR1
DR2
DR3
DR4
DR5
DR6
FIGURE 32. DATARDY WAVEFORMS WHEN |r| (MAGNITUDE) IS SELECTED AS AOUT
1 + FIR Delay
BOUT
Q0
Q1
Q2
Q3
Q4
Qn
Qn+1
Qn+2
AOUT
PROCCLK
f0 (R = 4)
DATARDY
DR-1
DR0
NOTE: I and Q are sample aligned in time. |r| and φ are sample aligned in time, but one sample delayed from I or Q. The frequency sample
is delayed in time from I or Q by 1 sample time + 63 tap FIR impulse response. If the FIR is set to decimate and frequency is selected
for AOUT, the DATARDY signal will be at the discriminator FIR output (decimated) rate.
FIGURE 33. DATARDY WAVEFORMS WHEN f (FREQUENCY) IS SELECTED AS AOUT
33
FN4450.4
May 1, 2007
相关PDF资料 |
PDF描述 |
|---|---|
| HSP50216KIZ | IC DOWNCONVERTER DGTL 4CH 196BGA |
| HSP50415VIZ | IC MODULATOR PROGRAMABLE 100MQFP |
| HSSLS-CALBL-013 | HEATSINK 48W SPOT OSRAM PREVALED |
| HSSLS-CALCL-005 | HEATSINK 21W SPOT PHILIPS SLM |
| HSSLS-CALCL-013 | HEATSINK 48W DOWNLIGHT 140 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital UpConverter |
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