- 您现在的位置：买卖IC网 > Datasheet目录441 > HSP50214BVIZ (Intersil)IC DOWNCONVERTER 14BIT 120-MQFP Datasheet资料下载
参数资料
| 型号： | HSP50214BVIZ |
| 厂商： | Intersil |
| 文件页数： | 37/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
HSP50214B
CONTROL WORD 19, BITS 24-21 = 011
(3 DATA WORDS IN EACH SERIAL OUTPUT)
DATA WORD 3
DATA WORD 2
DATA WORD 1
MAGNITUDE
DATA WORD 3
TBD
Q
DATA WORD 2
MAGNITUDE
I
DATA WORD 1
Q
SEROUTA
SEROUTB
THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE:
PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR
NOTE: Once magnitude is identified to follow Q,
it must be that way on both serial outputs.
FIGURE 35. EXAMPLE 2 SERIAL OUTPUT DATA STREAM
“NORMAL”
0
1
2
LATE
SERSYNC FOLLOWS LSB
SERSYNC
“INVERTED”
“NORMAL”
1
0
2
1
3
2
MODE
EARLY
SERSYNC PRECEDES MSB
SERSYNC
“INVERTED”
LSB WORD0
1
MSB WORD1
2
MSB WORD2
3
MSB WORD3
MODE
2
1
0
15
14
???
2
1
0
15
14
???
2
1
0
15
14
???
2
DATA SHIFT MSB FIRST
LSB WORD1
LSB WORD2
FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS
The serial direct output can be programmed to output less
TABLE 16. RAM DATA STORAGE MAP
than 16-bits. New output data preempts old output data, so if
SERSYNC is programmed to precede the MSB, then data
will shift out until new data comes along. Note that if
SERSYNC is programmed to follow the LSB, then a sync will
never occur.
Buffer RAM Output Port
The Buffer RAM parallel output mode utilizes a RAM to store
output data for future retrieval by either the 8-bit
microprocessor that is configuring the PDC or by a 16-bit
baseband processing engine (which could also be a
RAM
SAMPLE
SET
0
1
2
3
4
5
6
I
DATA
(000)
I 0 (15:0)
I 1 (15:0)
I 2 (15:0)
I 3 (15:0)
I 4 (15:0)
I 5 (15:0)
I 6 (15:0)
Q
DATA
(001)
Q 0 (15:0)
Q 1 (15:0)
Q 2 (15:0)
Q 3 (15:0)
Q 4 (15:0)
Q 5 (15:0)
Q 6 (15:0)
|r|
DATA
(010)
|r| 0 (15:0)
|r| 1 (15:0)
|r| 2 (15:0)
|r| 3 (15:0)
|r| 4 (15:0)
|r| 5 (15:0)
|r| 6 (15:0)
Φ
DATA
(011)
φ 0 (15:0)
φ 1 (15:0)
φ 2 (15:0)
φ 3 (15:0)
φ 4 (15:0)
φ 5 (15:0)
φ 6 (15:0)
F
DATA
(100)
f 0 (15:0)
f 1 (15:0)
f 2 (15:0)
f 3 (15:0)
f 4 (15:0)
f 5 (15:0)
f 6 (15:0)
microprocessor). Data is output from the RAM only on request
and can be obtained from either the 8-bit μ P interface or from
a 16-bit interface that uses the two LSBytes of AOUT and
BOUT. The RAM holds up to eight 80-bit sample sets. Each
sample set includes 16-bits of each I, Q, magnitude, phase,
and frequency data. The RAM samples are mapped as shown
in Table 16. The Buffer RAM controller supports both FIFO
and Snapshot modes.
37
7 I 7 (15:0) Q 7 (15:0) |r| 7 (15:0) φ 7 (15:0) f 7 (15:0)
NOTE: I and Q are sample aligned in time. |r| and φ are sample
aligned in time, but one sample delayed from I or Q. The
frequency sample is delayed in time from I or Q by 1
sample time + 63 tap FIR impulse response. If the FIR is
set to decimate, the FIR output will be repeated every
sample time until a new value appears at the filter output.
(i.e., the frequency samples are clocked out at the I, Q
sample rate regardless of decimation.)
FN4450.4
May 1, 2007
相关PDF资料 |
PDF描述 |
|---|---|
| HSP50216KIZ | IC DOWNCONVERTER DGTL 4CH 196BGA |
| HSP50415VIZ | IC MODULATOR PROGRAMABLE 100MQFP |
| HSSLS-CALBL-013 | HEATSINK 48W SPOT OSRAM PREVALED |
| HSSLS-CALCL-005 | HEATSINK 21W SPOT PHILIPS SLM |
| HSSLS-CALCL-013 | HEATSINK 48W DOWNLIGHT 140 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital UpConverter |
发布紧急采购，3分钟左右您将得到回复。