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参数资料
| 型号： | HSP50214BVIZ |
| 厂商： | Intersil |
| 文件页数： | 51/62页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER 14BIT 120-MQFP |
| 标准包装： | 24 |
| 功能： | 降频器 |
| RF 型： | AMPS，CDMA，GSM，TDMA |
| 封装/外壳： | 120-BQFP |
| 包装： | 托盘 |
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HSP50214B
CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-8
7-0
FUNCTION
Reserved
Timing NCO Phase
Offset
DESCRIPTION
Reserved.
These bits are used to offset the phase of the Timing NCO. The range is 0 to 1 times the resampler input
period interpreted either as ± T/2 (2’s complement) or 0 to T (offset binary). Bit 7 is the MSB. This location
is a holding register. After loading, a transfer to the Active Register is done by writing to Control Word 15
or by generating a SYNCIN2 with Control Word 11, Bit 5 set to 1.
CONTROL WORD 14: TIMING FREQUENCY STROBE (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
N/A
FUNCTION
Timing Frequency
Strobe
DESCRIPTION
Writing to this address updates the active timing NCO Frequency Register in the timing NCO (see Timing
NCO Section).
CONTROL WORD 15: TIMING PHASE STROBE (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
N/A
FUNCTION
Timing Phase Strobe
DESCRIPTION
Writing to this address updates the active timing NCO Phase Offset Register in the timing NCO (see
Timing NCO Section).
CONTROL WORD 16: RESAMPLING FILTER CONTROL (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
31-12
11-4
3
2-0
FUNCTION
Reserved
Re-Sampler Output
Pulse Delay
Re-Sampler Bypass
Filter Mode Select;
2- HB2 Enabled
1- HB1 Enabled
0- Re-Sampler
Enabled
51
DESCRIPTION
Reserved.
NOTE: These bits program the delay between output samples when interpolating. The extra outputs can
be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255 clocks of delay. A
delay of 0 or 1 is an invalid mode. When interpolating by 2, one extra output is generated; when
interpolating by 4, 3 extra outputs are generated. Program by the equation (PROCCLK/f OUT ) - 1.
Bit 11 is the MSB.
NOTE: If less than 5 is programmed, there will not be sufficient time to fully update the output
buffer. If less than 16 is programmed, the serial output may be preempted. This means that
it won’t finish and if the sync is programmed to follow the data, there may never be a sync.
0- Resampling Filter Enabled. A valid combination of bits 2-0 must also be selected.
1- Resampling Filter Section (including Interpolation halfband filters) is bypassed.
000- Not Valid.
001- Re-Sampler Enabled.
010- Halfband 1 Enabled.
011- Re-Sampler and Halfband Filter 1 Enabled.
100- Not Valid.
101- Not Valid.
110- Both Halfband Filters Enabled.
111- Re-Sampler and Both Halfband Filters Enabled.
FN4450.4
May 1, 2007
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相关代理商/技术参数 |
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|---|---|
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital UpConverter |
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