- 您现在的位置：买卖IC网 > PDF目录1924 > IDT82P2828BHG (IDT, Integrated Device Technology Inc)IC LIU T1/J1/E1 28+1CH 640-PBGA PDF资料下载
参数资料
| 型号： | IDT82P2828BHG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 114/154页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 标准包装： | 5 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 640-BGA 裸露焊盘 |
| 供应商设备封装： | 640-PBGA-EP（31x31） |
| 包装： | 托盘 |
| 其它名称： | 82P2828BHG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页当前第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
62
February 6, 2009
3.6.2
CLOCK OUTPUTS ON REFA/REFB
The outputs on REFA and REFB can be enabled or disabled, as
determined by the REFA_EN bit (b6, REFA) and the REFB_EN bit (b6,
REFB) respectively.
When the output is disabled, REFA/REFB is in High-Z state.
When the output is enabled, the output of REFA and REFB varies in
different operations. Refer to below for detailed description. Refer to
options in normal operation.
3.6.2.1 REFA/REFB in Clock Recovery Mode
In this mode (default), the clock of REFA and REFB is derived from
the recovered clock of one of the 29 channels as selected by the
REFA[4:0] bits (b4~0,REFA) and REFB[4:0] bits (b4~0,REFB). Deter-
mined by the FS_BYPAS bit (b4, REFCF) a Frequency Synthesizer can
be enabled for REFA (refer to Section 3.6.2.2 Frequency Synthesizer for
REFA Clock Output). If the Frequency Synthesizer is disabled, REFA
will output the recovered 1.544 MHz (T1) or 2.048 MHz (E1) clock
depending on the line mode of the selected channel. REFB output the
recovered 1.544 MHz (T1) or 2.048 MHz (E1) clock depending on the
line mode of the selected channel.
The recovered line clock can be output to REFA and REFB before or
after it passed the receive Jitter Attenuator (RJA) selected by the
JA_BYPAS bit (b6, REFCF).
3.6.2.2 Frequency Synthesizer for REFA Clock Output
For REFA a Frequency Synthesizer can be enabled or bypassed
(default) as selected by FS_BYPASS bit (b4, REFCF). The output
frequency is selected by the FREQ[2:0] bits (b2~0, REFCF). Frequen-
cies supported are 8 KHz, 64 KHz, 2.048 MHz, 4.096 MHz, 8.192 MHz,
19.44 MHz or 32.768 MHz.
3.6.2.3 Free Run Mode for REFA Clock Output
REFA can also be selected to provide a free running clock locked to
MCLK. To enable this mode the Frequency Synthesizer has to be
enabled by setting the FS_BYPAS bit (b4, REFCF) to ‘0’, and the FREE
bit (b3, REFCF) has to be set to ‘1’. REFA will provide a frequency
clock locked to MCLK.
3.6.2.4 REFA/REFB Driven by External CLKA/CLKB Input
In this mode, the clock of REFA and REFB is driven from an external
clock input of CLKA and CLKB respectively. CLKA and CLKB are
selected as an input source by setting REFA[4:0] bits (b4~0, REFA) and
REFB[4:0] bits (b4~0, REFB) to any value from ‘11101’ to ‘11111’.
CLKA and CLKB are an external T1/J1 (1.544 MHZ) or E1 (2.048
MHz) Clock Input. The CKA_T1E1 bit (b5, REFA) and CKB_T1E1 bit
(b5, REFB) should be set to match the input clock frequency.
Determined by the FS_BYPASS bit (b4, REFCF), a Frequency
Synthesizer can be enabled for REFA (refer to Section 3.6.2.2
Frequency Synthesizer for REFA Clock Output). If the Frequency
Synthesizer is disabled, REFA will output the 1.544 MHz (T1) or 2.048
MHz (E1) clock depending the CLKA input clock. REFB will output 1.544
MHz (T1) or 2.048 MHz (E1) depending on the CLKB input clock.
3.6.2.5 REFA and REFB in Loss of Signal (LOS) or Loss of Clock
Condition
If the recovered clock of one of the 29 channels is selected as the
clock source for REFA and REFB (refer to Section 3.6.2.1 REFA/REFB
in Clock Recovery Mode) and Line LOS (LLOS) is detected in the corre-
sponding channel, the state of output on REFA and REFB can be
selected by the REFH bit (b5, REFCF). If REFH is set to ‘1’, REFA and
REFB will output a high level in case of LLOS. If REFH is set to ‘0’ and
LLOS is detected, REFA and REFB clock outputs will be locked to
MCLK while the selected clock frequency will remain unchanged.
LLOS condition is set when LLOS_S bit (b0, STAT0) is ‘1’. Refer to
Refer to Figure-42 for a detailed overview of REFA output in case of
LLOS. REFB output option is only determined by the REFH bit (b5,
REFCF) to be locked to MCLK or set to high level output.
If CLKA is selected as the clock source for REFA (refer to
there is no clock input on CLKA for more than 8 T1 clock cycles if T1
mode is selected (i.e. CKA_T1E1 bit (b5, REFA) is ‘0’) or more than 8 E1
clock cycles if E1 mode is selected (i.e. CKA_T1E1 bit (b5, REFA) is ‘1’),
the state of the REFA output is determined by the FS_BYPAS bit (b4,
sizer is disabled (i.e. FS_BYPAS bit (b4, REFCF) is ‘0’). REFA will
output a high level. If the Frequency Synthesizer is enabled and the
FREE bit (b3, REFCF) is set to ‘0’, REFA will output a high level. If the
Frequency Synthesizer is enabled and the FREE bit (b3, REFCF) is set
to ‘1’, REFA will be locked to MCLK.
Refer to Figure-43 for a detailed overview of REFA output in case of
loss of CLKA.
If CLKB is selected as the clock source for REFB (refer to section
there is no clock input on CLKB for more than 8 T1 clock cycles if T1
mode is selected (i.e. CKB_T1E1 bit (b5, REFB) is ‘0’) or more than 8
E1 clock cycles if E1 mode is selected (i.e. CKB_T1E1 bit (b5, REFB) is
‘1’), the output on REFB is determined by the REFH bit (b5, REFCF). If
REFH is set to ‘1’, REFB will output a high level. If REFH is set to ‘0’, the
REFB clock output will be locked to MCLK.
1. ‘000’ and ‘011’ are reserved for FREQ[2:0] in this mode.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT82P2916BFG | IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088BBG | IC LIU T1/E1/J1 OCTAL 256PBGA |
| IDT82V2041EPPG | IC LIU T1/J1/E1 1CH 44-TQFP |
| IDT82V2042EPFG | IC LIU T1/J1/E1 2CH SHORT 80TQFP |
| IDT82V2044EPFG | IC LIU T1/E1 QUAD SHORT 128-TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82P2916 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2916BFG | 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA RoHS:是 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| IDT82P2916BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
| IDT82P5088BBBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
发布紧急采购，3分钟左右您将得到回复。