参数资料
型号: IDT82P2828BHG
厂商: IDT, Integrated Device Technology Inc
文件页数: 95/154页
文件大小: 0K
描述: IC LIU T1/J1/E1 28+1CH 640-PBGA
标准包装: 5
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 640-BGA 裸露焊盘
供应商设备封装: 640-PBGA-EP(31x31)
包装: 托盘
其它名称: 82P2828BHG
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
45
February 6, 2009
3.5.3.2 System LOS (SLOS)
SLOS can only be detected when the transmit system interface is in
Dual Rail NRZ Format mode or in Dual Rail RZ Format mode.
The amplitude and density of the data input from the transmit system
side are monitored. When the input ‘0’s are equal to or more than N
consecutive pulse intervals, SLOS is declared. When the average
density of marks is at least 12.5% for M consecutive pulse intervals
starting with a mark, SLOS is cleared. Here N and M are defined by the
LAC bit (b7, LOS,...). Refer to Table-18 for details.
In T1/J1 mode, SLOS detection supports ANSI T1.231 and I.431. In
E1 mode, SLOS detection supports G.775 and ETSI 300233/I.431. The
criteria are selected by the LAC bit (b7, LOS,...).
When SLOS is detected, the SLOS_S bit (b1, STAT0,...) will be set. A
transition from ‘0’ to ‘1’ on the SLOS_S bit (b1, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the SLOS_S bit (b1, STAT0,...) will
set the SLOS_IS bit (b1, INTS0,...) to ‘1’, as selected by the LOS_IES bit
(b1, INTES,...). When the SLOS_IS bit (b1, INTS0,...) is ‘1’, an interrupt
will be reported by INT if not masked by the SLOS_IM bit (b1, INTM0,...).
SLOS may be counted by an internal Error Counter or may be indi-
cated by the TMFn pin. Refer to Section 3.5.6 Error Counter and
Table-18 SLOS Criteria
Operation
Mode
LAC
Criteria
SLOS Declaring 1
SLOS Clearing 1
T1/J1
0
ANSI T1.231
no pulse detected for N consecutive pulse intervals,
N = 175 bits
12.5% mark density with less than 100 consecutive
zeros for M consecutive pulse intervals,
M = 175 bits
1
ANSI I.431
no pulse detected for N consecutive pulse intervals,
N = 1544 bits
12.5% mark density with less than 100 consecutive
zeros for M consecutive pulse intervals,
M = 175 bits
E1
0
G.775
no pulse detected for N consecutive pulse intervals,
N = 32 bits
12.5% mark density with less than 16 consecutive
zeros for M consecutive pulse intervals,
M = 32 bits
1
ETSI 300233/
I.431
no pulse detected for N consecutive pulse intervals,
N = 2048 bits
12.5% mark density with less than 16 consecutive
zeros for M consecutive pulse intervals,
M = 32 bits
Note:
1. System input ports are schmitt-trigger inputs)
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