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参数资料
| 型号： | IDT82P2828BHG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 92/154页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 标准包装： | 5 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 640-BGA 裸露焊盘 |
| 供应商设备封装： | 640-PBGA-EP（31x31） |
| 包装： | 托盘 |
| 其它名称： | 82P2828BHG |
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IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
42
February 6, 2009
3.4
JITTER ATTENUATOR (RJA & TJA)
Two Jitter Attenuators are provided for each channel of receiver and
transmitter. Each Jitter Attenuator can be enabled or disabled, as deter-
mined by the RJA_EN/TJA_EN bit (b3, RJA/TJA,...) respectively.
Each Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Figure-23 Jitter Attenuator
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]/
TJA_DP[1:0] bits (b2~1, RJA/TJA,...). Accordingly, the typical delay
produced by the Jitter Attenuator is 16 bits, 32 bits or 64 bits. The 128-
bit FIFO is used when large jitter tolerance is expected, while the 32-bit
FIFO is used in delay sensitive applications.
The DPLL is used to generate a de-jittered clock to clock out the data
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF) by 20 dB per decade
falling off. The jitter whose frequency is lower than the CF passes
through the DPLL without any attenuation. In T1/J1 applications, the CF
of the DPLL is 5 Hz or 1.26 Hz. In E1 applications, the CF of the DPLL is
6.77 Hz or 0.87 Hz. The CF is selected by the RJA_BW/TJA_BW bit (b0,
RJA/TJA,...). The lower the CF is, the longer time is needed to achieve
synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow and underflow are both captured
by the RJA_IS/TJA_IS bit (b5/6, INTS0,...). The occurrence of overflow
or underflow will be reported by the INT pin if enabled by the RJA_IM/
TJA_IM bit (b5/6, INTM0,...).
To avoid overflow or underflow, the JA-Limit function can be enabled
Limit function is enabled, the speed of the outgoing data will be adjusted
automatically if the FIFO is 2-bit close to its full or emptiness. Though
the JA-Limit function can reduce the possibility of FIFO overflow and
underflow, the quality of jitter attenuation is deteriorated.
The performance of the Jitter Attenuator meets ITUT I.431, G.703,
G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/13, AT&T
TR62411, TR43802, TR-TSY 009, TR-TSY 253 and TR-TRY 499. Refer
to Section 8.12 Jitter Attenuation Characteristics for the jitter perfor-
mance.
FIFO
32/64/128
DPLL
Jittered Data
De-jittered Data
Jittered Clock
De-jittered Clock
write
clock
read
clock
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相关代理商/技术参数 |
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| IDT82P2916 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
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