参数资料
型号: IDT82P2828BHG
厂商: IDT, Integrated Device Technology Inc
文件页数: 45/154页
文件大小: 0K
描述: IC LIU T1/J1/E1 28+1CH 640-PBGA
标准包装: 5
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 640-BGA 裸露焊盘
供应商设备封装: 640-PBGA-EP(31x31)
包装: 托盘
其它名称: 82P2828BHG
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications
139
February 6, 2009
8.13 MICROPROCESSOR INTERFACE TIMING
8.13.1 SERIAL MICROPROCESSOR INTERFACE
A falling transition on CS indicates the start of a read/write operation,
and a rising transition indicates the end of the operation. After CS is set
to low, a 5-bit instruction on SDI is input to the device on the rising edge
of SCLK. If the MSB is ‘1’, it is a read operation. If the MSB is ‘0’, it is a
write operation. Following the instruction, an 11-bit address is clocked in
on SDI to specify the register. If the device is in a read operation, the
data read from the specified register is output on SDO on the falling
edge of SCLK (refer to Figure-59). If the device is in a write operation,
the data written to the specified register is input on SDI following the
address byte (refer to Figure-60).
Figure-59 Read Operation in Serial Microprocessor Interface
Figure-60 Write Operation in Serial Microprocessor Interface
CS
SCLK
SDI
SDO
10
0
1
2
3
4
5
6
7
8
9
111213 141516 1718192021 22 23
A0
A7 A6 A5 A4 A3 A2 A1
Instruction
Register Address
High-Z
D0
D7 D6 D5 D4 D3 D2 D1
Don't-Care
A9
R/W
Don't Care
A10
A8
CS
SCLK
SDI
SDO
10
0
1
2
3
4
5
6
7
8
9
11 12 13 14 15 16 17 18 19 20 21 22 23
A0
A7 A6 A5 A4 A3 A2 A1
Instruction
Data Byte
High-Z
D0
D7 D6 D5 D4 D3 D2 D1
Register Address
A8
R/W
Don't Care
A10 A9
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