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参数资料
| 型号： | IDT82P2828BHG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 137/154页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 标准包装： | 5 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 640-BGA 裸露焊盘 |
| 供应商设备封装： | 640-PBGA-EP（31x31） |
| 包装： | 托盘 |
| 其它名称： | 82P2828BHG |
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IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Programming Information
83
February 6, 2009
CLKG - CLKT1 & CLKE1 Generation Control Register
REFCF - REFA/B Output Configuration Register
Address: 1C0H
Type: Read / Write
Default Value: 0FH
Bit
Name
Description
7 - 4
-
Reserved.
3
CLKE1_EN
This bit controls whether the output on the CLKE1 pin is enabled.
0: The output is disabled. CLKE1 is in High-Z state.
1: The output is enabled. The frequency of CLKE1 is determined by the CLKE1 bit (b2, CLKG). (default)
2
CLKE1
This bit is valid only when the CLKE1_EN bit (b3, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKE1 pin.
0: 8 KHz.
1: 2.048 MHz. (default)
1
CLKT1_EN
This bit controls whether the output on the CLKT1 pin is enabled.
0: The output is disabled. CLKT1 is in High-Z state.
1: The output is enabled. The frequency of CLKT1 is determined by the CLKT1 bit (b0, CLKG). (default)
0
CLKT1
This bit is valid only when the CLKT1_EN bit (b1, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKT1 pin.
0: 8 KHz.
1: 1.544 MHz. (default)
Address: 200H
Type: Read / Write
Default Value: 30H
Bit
Name
Description
7-
Reserved.
6
JA_BYPAS
This bit is valid only when the clock source for REFA or REFB is the recovered clock of one of the 29 channels in the correspond-
ing receiver. This bit determines whether the selected recovered clock passes through the RJA.
0: The selected recovered clock is derived from the output of RJA. (default)
1: The selected recovered clock does not pass through the RJA and is derived from the output of Rx Clock & Data Recovery.
5
REFH
This bit is valid only when the selected clock source is lost. This bit controls the output on REFA/REFB.
For REFA, this bit, together with the FS_BYPAS bit (b4, REFCF) and the FREE bit (b3, REFCF), controls the output on REFA
when the selected clock source is the recovered clock of one of the 29 channels; this bit is ignored when the selected clock
source is CLKA. Refer to the related table in the description of the FREE bit (b3, REFCF).
For REFB:
0: Output free running clock. The frequency is 1.544 MHz if the selected clock source was T1 clock or 2.048 MHz if the selected
clock source was E1 clock.
1: Output high level. (default)
4
FS_BYPAS
This bit determines whether the selected clock source for REFA passes through an internal Frequency Synthesizer.
0: The internal Frequency Synthesizer is enabled.
1: The internal Frequency Synthesizer is bypassed. (default)
7
654
321
0
-
CLKE1_EN
CLKE1
CLKT1_EN
CLKT1
7654321
0
-
JA_BYPAS
REFH
FS_BYPAS
FREE
FREQ2
FREQ1
FREQ0
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相关代理商/技术参数 |
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|---|---|
| IDT82P2916 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2916BFG | 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA RoHS:是 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| IDT82P2916BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
| IDT82P5088BBBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
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