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| 型号： | IDT88P8341BHI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHI |
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IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Table of Contents
Features ........................................................................................................................................................................................................................ 1
Applications .................................................................................................................................................................................................................. 1
1. Introduction ............................................................................................................................................................................................................. 8
2. Pin description ......................................................................................................................................................................................................... 9
3. External interfaces ................................................................................................................................................................................................. 13
3.1 SPI-3 ............................................................................................................................................................................................................... 13
3.1.1 SPI-3 ingress ........................................................................................................................................................................................ 13
3.1.2 SPI-3 egress ........................................................................................................................................................................................ 15
3.2 SPI-4 ............................................................................................................................................................................................................... 17
3.2.1 SPI-4 ingress ........................................................................................................................................................................................ 17
3.2.2 SPI-4 egress ........................................................................................................................................................................................ 20
3.2.3 SPI-4 startup handshake ....................................................................................................................................................................... 20
3.3 Microprocessor interface .................................................................................................................................................................................. 22
4. Datapath and flow control .................................................................................................................................................................................... 23
4.1 SPI-3 to SPI-4 datapath and flow control .......................................................................................................................................................... 25
4.2 SPI-4 to SPI-3 datapath and flow control .......................................................................................................................................................... 30
4.3 Microprocessor interface to SPI-3 datapath ...................................................................................................................................................... 33
4.3.1 SPI-3 to ingress microprocessor interface datapath ................................................................................................................................33
4.3.2 Microprocessor insert to SPI-3 egress datapath ..................................................................................................................................... 34
4.3.3 Microprocessor interface to SPI-4 egress datapath ................................................................................................................................ 35
4.3.4 SPI-4 ingress to microprocessor interface datapath ................................................................................................................................36
5. Performance monitor and diagnostics ................................................................................................................................................................. 37
5.1 Mode of operation ............................................................................................................................................................................................ 37
5.2 Counters ......................................................................................................................................................................................................... 37
5.2.1 LID associated event counters ............................................................................................................................................................... 37
5.2.2 Non - LID associated event counters ..................................................................................................................................................... 37
5.3 Captured events .............................................................................................................................................................................................. 37
5.3.1 Non LID associated events .................................................................................................................................................................... 37
5.3.2 LID associated events ........................................................................................................................................................................... 37
5.3.2.1 Non critical events ...................................................................................................................................................................... 37
5.3.2.2 Critical events ............................................................................................................................................................................. 37
5.3.3 Timebase .............................................................................................................................................................................................. 37
5.3.3.1 Internally generated timebase ..................................................................................................................................................... 37
5.3.3.2 Externally generated timebase .................................................................................................................................................... 37
6. Clock generator ...................................................................................................................................................................................................... 38
7. Loopbacks .............................................................................................................................................................................................................. 39
7.1 SPI-3 Loopback ............................................................................................................................................................................................... 39
8. Operation guide ..................................................................................................................................................................................................... 40
8.1 Hardware operation ........................................................................................................................................................................................ 40
8.1.1 System reset ......................................................................................................................................................................................... 40
8.1.2 Power on sequence .............................................................................................................................................................................. 40
8.1.3 Clock domains ...................................................................................................................................................................................... 40
8.2 Software operation ........................................................................................................................................................................................... 40
8.2.1 Chip configuration sequence ................................................................................................................................................................. 40
8.2.2 Logical Port activation and deactivation .................................................................................................................................................. 41
8.2.3 Buffer segment modification .................................................................................................................................................................... 41
8.2.4 Manual SPI-4 ingress LVDS bit alignment .............................................................................................................................................. 41
8.2.5 SPI-4 status channel software ............................................................................................................................................................... 42
8.2.6 IDT88P8341 layout guidelines .............................................................................................................................................................. 42
8.2.7 Software Eye-Opening Check on SPI-4 Interface .................................................................................................................................. 43
9. Register description .............................................................................................................................................................................................. 45
9.1 Register access summary ................................................................................................................................................................................ 45
9.1.1 Direct register format ............................................................................................................................................................................. 45
9.1.2 Indirect register format ........................................................................................................................................................................... 45
9.2 Direct access registers ..................................................................................................................................................................................... 49
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| IDT88P8344BHI | IC SPI3-SPI4 EXCHANGE 820-PBGA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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