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| 型号： | IDT88P8341BHI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 34/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHI |
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IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
List of Figures
Figure 1. Typical application: optical port and NPU/Traffic Manager .................................................................................................................................. 8
Figure 2. Data Path Diagram ........................................................................................................................................................................................... 8
Figure 3. Link mode SPI-3 ingress interface ................................................................................................................................................................... 14
Figure 4. PHY mode SPI-3 ingress interface .................................................................................................................................................................. 14
Figure 5. Link mode SPI-3 egress interface .................................................................................................................................................................... 16
Figure 6. PHY mode SPI-3 egress interface ................................................................................................................................................................... 16
Figure 7. Data sampling diagram ................................................................................................................................................................................... 18
Figure 8. SPI-4 ingress state diagram ............................................................................................................................................................................ 19
Figure 9. SPI-4 egress status state diagram ................................................................................................................................................................... 21
Figure 10. Interrupt scheme ........................................................................................................................................................................................... 22
Figure 11. Definition of data flows ................................................................................................................................................................................... 23
Figure 12. Logical view of datapath configuration using PFPs ......................................................................................................................................... 24
Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor ............................................................................................................................. 25
Figure 14. SPI-3 ingress LP to LID map ........................................................................................................................................................................ 27
Figure 15. SPI-4 egress LID to LP map ......................................................................................................................................................................... 28
Figure 16. SPI-3 ingress to SPI-4 egress datapath ........................................................................................................................................................ 28
Figure 17. SPI-3 ingress to SPI-4 egress flow control path ............................................................................................................................................. 29
Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor ............................................................................................................................. 30
Figure 19. SPI-4 ingress to SPI-3 egress datapath ........................................................................................................................................................ 31
Figure 20. SPI-4 ingress to SPI-3 egress flow control ..................................................................................................................................................... 32
Figure 21 . Microprocessor data capture buffer .............................................................................................................................................................. 33
Figure 22. SPI-3 ingress to microprocessor capture interface datapath ........................................................................................................................... 33
Figure 24. Microprocessor interface to SPI-3 egress detailed datapath diagram .............................................................................................................. 34
Figure 23. Microprocessor data insert buffer .................................................................................................................................................................. 34
Figure 25. Microprocessor data insert buffer .................................................................................................................................................................. 35
Figure 26. Microprocessor data insert interface to SPI-4 egress datapath ....................................................................................................................... 35
Figure 27. Microprocessor data capture buffer ............................................................................................................................................................... 36
Figure 28. SPI-4 ingress to microprocessor data capture interface path .......................................................................................................................... 36
Figure 29. Clock generator ............................................................................................................................................................................................ 38
Figure 30. SPI-3 Loopback diagram .............................................................................................................................................................................. 39
Figure 31. Power-on-Reset Sequence .......................................................................................................................................................................... 40
Figure 32. DDR interface and eye opening check through over sampling ....................................................................................................................... 43
Figure 33. Direct & indirect access ................................................................................................................................................................................. 45
Figure 34. SPI-3 I/O timing diagram ............................................................................................................................................................................... 80
Figure 35. SPI-4 I/O timing diagram ............................................................................................................................................................................... 81
Figure 36. Microprocessor parallel port Motorola read timing diagram ............................................................................................................................ 83
Figure 37. Microprocessor parallel port Motorola write timing diagram ............................................................................................................................ 84
Figure 38. Microprocessor parallel port Intel mode read timing diagram .......................................................................................................................... 85
Figure 39. Microprocessor parallel port Intel mode write timing diagram .......................................................................................................................... 86
Figure 40. Microprocessor serial peripheral interface timing diagram .............................................................................................................................. 87
Figure 41. IDT88P8341 820PBGA package, bottom view .............................................................................................................................................. 92
Figure 42. IDT88P8341 820PBGA package, top and side views .................................................................................................................................... 93
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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