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| 型号： | IDT88P8341BHI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 52/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHI |
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56
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
0=Odd parity on this port
1=Even parity on this port
PARITY_EN TheSPI-3interfaceisprovisionedtoenableordisableparity
generation and checking, according to the state of the EVEN_PARITY bit.
0=Disable parity on this SPI-3 port
1=Enable parity on this SPI-3 port
WATERMARK
The SPI-3 interface can be set to a SPI-3 ingress port
watermark value. The value of 0x10 is the highest watermark that can be set,
meaning all ingress buffers will be full before backpressure will be initiated on
the SPI-3 ingress interface. The WATERMARK field value of 0x08 is used to
setthewatermarkforahalf-fullingressbufferbeforetrippingbackpressure.The
units of WATERMARK are one-sixteenth of the available ingress buffering per
unit. Each unit is equal to 128 bytes. BACKPRESSURE_EN must be set
[Register_offset 0x01] for the watermark to become effective. The watermark
field is usually set to 0x10, and the FREE_SEGMENT field of Table 75, SPI-
3 ingress port descriptor tables (Block_base 0x1200) is used for per LID
backpressure.
SPI-3 ingress configuration register (Block_base
0x0200 + Register_offset 0x01)
ThereisoneSPI-3ingressconfigurationregisterfortheSPI-3interface.The
register has read and write access.
The bit fields for the SPI-3 ingress configuration register are described in the
following paragraphs.
BACKPRESSURE_EN
the SPI-3 interface can have backpressure
enabled or disabled. Disabling backpressure means that data coming into the
ingress may be lost if the SPI-3 interface ingress buffers overflow. The SPI-3
interface can run at full-rate, however, since there will be no backpressure.
Attached devices that do not respond properly to backpressure should be
interfaced by disabling backpressure.
Enabling backpressure will cause the I_ENB signal to be asserted when the
ingressbufferfilllevelisequaltotheWATERMARKvalue[Register_offset0x00],
orthefreesegmentbufferthresholdTable75,SPI-3ingressportdescriptortable
(Block_base 0x1200) has been reached for any active LID.
0=Disable backpressure on the SPI-3 ingress.
1=Enable backpressure on the SPI-3 ingress interface.
FIX_LP
TheSPI-3interfacecanfixthelogicalportaddressto0x00.This
is useful when there is only one LP on an interface, such as with some single-
PHY devices.
0=Donotfixlogicalportaddressto0x00,butusetheactual
LP found in the packet fragments.
1= Fix logical port address to 0x00
SPI-3 ingress fill level register (Block_base 0x0200
+ Register_offset 0x02)
TABLE 51 - SPI-3 INGRESS CONFIGURATION
REGISTER(REGISTER_OFFSET=0x01)
Field
Bits
Length
Initial Value
BACKPRESSURE_EN
0
1
0b1
FIX_LP
1
0b0
Reserved
31:2
30
0x0000
ThereisoneregisterforSPI-3ingressfilllevelregisterfortheSPI-3interface.
The register has read-only access. The bit fields of the SPI-3 ingress fill level
register are described.
FILL_CUR
CurrentSPI-3ingressbufferfilllevel.Sincethisisareal-time
register, the value read from it will change rapidly and is used for internal
diagnosticsonly.
I_FCLK_AV Current SPI-3 ingress clock availability is checked here.
0=SPI-3 ingress clock not detected on a SPI-3 port
1=SPI-3ingressclocktransitionsdetectedonaSPI-3port
SPI-3 ingress max fill register (Block_base 0x0200
+ Register_offset 0x03)
TABLE 52 - SPI-3 INGRESS FILL LEVEL REGISTER
(REGISTER_OFFSET=0x02)
Field
Bits
Length
Initial Value
FILL_CUR
4:0
5
0x00
I_FCLK_AV
5
1
0b1
TABLE 53 - SPI-3 INGRESS MAX FILL LEVEL
REGISTER(REGISTER_OFFSET=0x03)
Field
Bits
Length
Initial Value
FILL_MAX
4:0
5
0x00
There is one register for SPI-3 ingress max fill level register per SPI-3
interface. Each register has read-only access, and is cleared after reading.
0x10isthehighestfillinglevel,meaningallingressbuffershadbeenfullatsome
time since the last read of the FILL_MAX field. The units of FILL_MAX are one-
sixteenthoftheavailableingressbuffering.Eachunitisequalto128bytes.The
bitfieldofaSPI-3ingressmaxfilllevelregisterisdescribed.TheTable53-SPI-
3 ingress max fill level register (Register_offset=0x03) is for diagnostics only.
FILL_MAX
Maximum SPI-3 ingress buffer fill level since the last read of
the SPI-3 ingress max fill level register.
9.3.3 Block base 0x0500 registers
SPI-3 egress LID to LP map (Block_base 0x0500 +
Register_offset 0x00-0x3F)
TABLE 54 - SPI-3 EGRESS LID TO LP MAP
Field
Bits
Length
Initial Value
LP
7:0
8
0x00
ENABLE
8
1
0b0
BIT_REVERSAL
9
1
0b0
There are 64 SPI-3 egress LID to LP maps for the SPI-3 interface, one per
potential SPI-3 LID.
The SPI-3 egress LID to LP maps have read and write access. The SPI-
3egressLIDtoLPmapsareusedtomapSPI-3egresslogicalidentifierstoSPI-
3logicalportaddressesthatarein-bandwiththeSPI-3egresspacketfragments.
LP
The LP programmed is associated to the LID with the same number
as the register address.
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相关代理商/技术参数 |
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|---|---|
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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