- 您现在的位置：买卖IC网 > PDF目录1924 > IDT88P8341BHI (IDT, Integrated Device Technology Inc)IC SPI3-SPI4 EXCHANGE 820-PBGA PDF资料下载
参数资料
| 型号： | IDT88P8341BHI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 51/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHI |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页当前第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
55
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
TABLE 50 - SPI-3 GENERAL CONFIGURATION
REGISTER(REGISTER_OFFSET=0x00)
Field
Bits
Length
Initial Value
LINK
0
1
0b0
PACKET
1
0b1
SPI3_ENABLE
2
1
0b0
BUSWIDTH
3
1
0b0
EVEN_PARITY
4
1
0b0
PARITY_EN
5
1
0b1
Reserved
6
1
0b0
Reserved
7
1
0b0
WATERMARK
12:8
5
0x0F
Reserved
31:13
19
0x000
9.3.1 Block base 0x0000 registers
SPI-3 ingress LP to LID map (Block_base 0x0000 +
Register_offset 0x00 to 0xFF)
TABLE 49 - SPI-3 INGRESS LP TO LID MAP
Field
Bits
Length
Initial Value
LID
5:0
6
0x00
ENABLE
6
1
0b0
BIT_REVERSAL
7
1
0b0
There are 256 SPI-3 ingress Logical Port (LP) to Logical Identifier (LID)
registers, one per potential SPI-3 LP. Only 64 LPs per SPI-3 physical interface
can be enabled. An attempt to enable more than 64 LPs per SPI-3 physical
interface or to assign an identical LID to more than one LP will be discarded
and an error code will be returned. The ENABLE bit is used to enable SPI-
3 logical ports. All data from non-enabled SPI-logical ports is discarded and
aninactiveSPI-3logicalporteventisgenerated.Thiseventisdirectedtowards
the PMON & DIAG module. Disabled ports always generate available status.
The Table 49 - SPI-3 ingress LP to LID Map assigns a LID to a SPI-3 logical
port. LID mapping for 64 out of 256 SPI-3 logical ports is supported on the SPI-
3 physical port. LPs in the SPI Exchange are 8 bits wide[7:0] and range from
0to255.AnexampleofmappingSPI-3physicalinterface,LP0x08toLID0x05,
activating the LID, and not using bit reversal is outlined.
Perform an indirect write of 0x45 to register address Module_base 0x0000
+ Block_base 0x0000 + Register_offset 0x08 = 0x0008.
The Initial Value column is the value of the register after reset.
LID
The LID programmed is associated to the LP with the same
number as the register address. Six bits support the 64 simultaneously active
LIDs on the SPI-3 physical interface.
ENABLE
This bit is used to enable or disable the connection of this LP
to this LID.
0=LID disabled
1=LID enabled
BIT_REVERSAL This bit is used to reverse the bit ordering of each byte
of the SPI-3 interface on a per-LID basis.
0=Disable bit reversal for this LID
1=Enable bit reversal for this LID
9.3.2 Block base 0x0200 registers
SPI-3 general configuration register (Block_base
0x0200 + Register_offset 0x00)
There is one register for SPI-3 general configuration for the SPI-3 interface.
The SPI-3 general configuration register has read and write access. The
address for the SPI-3 general configuration register is 0x0200. The bit fields of
the SPI-3 general configuration register are described in the following para-
graphs.
LINK A SPI-3 interface can be used either in Link or PHY modes. For
connectingtoatransmissionline-interfacePHY,programtheSPIExchangefor
Link mode. For connecting the SPI-3 interface to an NPU or other Link-mode
device, program the SPI-3 interface for PHY mode. The SPI-3 ingress and
egress of a given SPI-3 physical port will always be in the same mode.
0= SPI-3 interface in PHY mode
1= SPI-3 interface in Link mode
PACKET
A SPI-3 interface can be used either in BYTE or PACKET
modes.ASPI-3interfaceactingasaLinklayerdevicecanpolltheattachedPHY
deviceforupto64LPsiftheattachedPHYdevicesupportsthepollinginterface.
When attached to a PHY device that only supports byte mode, the four direct
status indicators can be used. When the SPI Exchange is in PHY mode, the
PACKET bit is used to select either a polled or direct status response to the
attached Link device.
0 = BYTE mode with direct status indication for up to 4 LPs [3:0]
1= PACKET mode with polled status for up to 64 LPs
SPI3_ENABLE TheSPI-3interfacecanbeenabledordisabledaccording
to the state programmed into this bit. A port should be disabled to save power
if it is not used.
0=SPI-3 Physical port disabled, outputs are in tristate
1=SPI-3 Physical port enabled
BUSWIDTH
The SPI-3 interface can be used as either a single 8-bit or
32-bitinterface,accordingtotheneedsoftheattacheddevice.TheSPI-3ingress
and egress of a given SPI-3 physical port will always be of the same bus width.
0=32 bit SPI-3 interface
1=8 bit SPI-3 interface
EVEN_PARITY The SPI-3 interface is provisioned to generate and to
checkforoddorevenparity.ThePARITY_ENbitmustbesetforthistobecome
effective. Odd parity is standard for SPI-3 interfaces.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT88P8342BHI | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| IDT88P8344BHI | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| IDT89H24NT24G2ZBHLG | IC PCI SW 24LANE 24PORT 324BGA |
| IDT89HPES16NT2ZBBCG | IC PCI SW 16LANE 2PORT 484-CABGA |
| IDT89HPES24NT3ZBBXG | IC PCI SW 24LANE 3PORT 420-SBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
发布紧急采购，3分钟左右您将得到回复。