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| 型号： | IDT88P8341BHI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 60/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHI |
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63
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Anexampleoftheuseofthebuffersegmentpoolfollows.ForaSPI-3ingress
interface that will never have more than four LIDs, set the NR_LID field for this
interfaceto0x01.Thisallows256buffersegmentsforaLID,withthetotalnumber
of buffer segments for all 4 LIDs equal to 508. Let’s say you want only 64 buffer
segments for one of the LIDs. Program field M for that LID to 0x040 (64 base
10). Let’s say you want to backpressure the SPI-3 ingress interface when 48
of the 64 allocated buffers for this LID are full. In other words, you want to exert
SPI-3 ingress backpressure when only 16 segments remain for this LID. Since
M=0x040, N=4 from the description of the M field above [Block_base 0x1200].
Setting the FREE_SEGMENT field to 4 then yields the desired THRESHOLD
of 16.
TABLE 77 - NR_LID FIELD ENCODING
NR_LID
Maximum Number
Maximum Buffer Segments
of LIDs
for a LID
0b000
1
508
0b001
4
256
0b010
8
128
0b011
16
64
0b100
32
0b101
64
16
SPI-3 to SPI-4 flow control register (Block_base
0x1300 + Register_offset 0x01)
TABLE 78 - SPI-3 TO SPI-4 FLOW CONTROL REG-
ISTER (REGISTER_OFFSET 0x01)
Field
Bits
Length
Initial Value
CREDIT_EN
0
1
0b1
BURST_EN
1
0b0
Reserved
7:3
6
0x00
The SPI-3 to SPI-4 flow control register has read and write access. There
is one SPI-3 to SPI-4 flow control register for the SPI-3 ingress.The bit fields of
the SPI-3 to SPI-4 flow control register are described.
CREDIT_EN
The information received over the FIFO status channel is
interpreted as status or credit information as selected by the CREDIT_EN flag
in the SPI-3 to SPI-4 flow control Register. If the status mode is used, data will
beegresseduntilthestatusischangedbytheattacheddevice.Ifthecreditmode
is used, the SPI-4 egress will issue only one credit’s worth data burst and then
waitforanothercreditfromthestatuschannelbeforeissuinganotherLIDburst.
0=Statusmode
1=Credit mode
BURST_EN
MultipleBurstEnableallowsmorethanonebursttobesent
to an LP. This feature is included to relieve systems with long latency between
updates. When this feature is not enabled, only one burst per LP is allowed into
the SPI-4 egress buffers.
0=Disable burst enable
1=Enable burst enable
FREE_SEGMENT The FREE_SEGMENT field is used to define the SPI-
3 ingress per-LID free segment backpressure threshold based on the number
of free buffer segments (M) available, as follows:
THRESHOLD = N * FREE_SEGEMENT,
Where the value of N is defined as a function of the domain of M:
M[8:0]
N (base 10)
0x1FC to 0x100
16
0x0FF to 0x080
8
0x07F to 0x040
4
0x03F to 0x020
2
0x01F to 0x000
1
TheTHRESHOLDthusdefinedisthenumberoffreesegmentsavailablefor
a LID at the time of backpressure initiation.
9.3.10 Block base 0x1300 registers
The SPI-3 ingress to SPI-4 egress Packet Fragment Processor and flow
control registers are at Block_Base 0x1300.
SPI-3 to SPI-4 PFP register (Block_base 0x1300 +
Register_offset 0x00)
TABLE 76 - SPI-3 TO SPI-4 PFP REGISTER
(REGISTER_OFFSET 0x00)
Field
Bits
Length
Initial Value
NR_LID
2:0
3
0b011
Reserved
7:3
5
0x0
ASPI-3ingresstoSPI-4egressPFP(PacketFragmentProcessor)Register
has read and write access. There is one SPI-3 to SPI-4 PFP Register per SPI-
3 ingress. The bit fields of a SPI-3 to SPI-4 PFP Register are described.
NR_LID The maximum number of LIDs per SPI-3 physical ingress
interface that will ever be used is programmed into the NR_LID field. Once
configured after reset, this value can not be changed. Fewer LIDs can be used
by not activating some of the LIDs, but more LIDs than the value in NR_LID are
not allowed and will generate an error. The NR_LID field is important, as the
buffersegmentpoolisdividedamongthenumberofLIDsprogrammedintothe
NR_LID field.
A 128 Kbyte SPI-3 to SPI-4 buffer segment pool for storing data bursts for
the SPI-4 egress is available for each SPI-3 physical port. A configurable part
ofthisbuffersegmentpoolcanbeassignedtoeachofthepossibleLIDsallowed
by the NR_LID field value per SPI-3 physical interface. The buffer size for a LID
can be configured in multiples (M) of 256 bytes. Modifications of the buffer size
allocatedtoaLIDaresupportedonlywhenthelogicalportassociatedtotheLID
is disabled. Attempts to allocate more memory than available will generate an
allocation error event. The indirect access module will discard the attempt.
A 128 Kbyte SPI-3 to SPI-4 buffer segment pool is divided into 508 buffer
segments.Eachbuffersegmentisequalto256bytes.Thebuffersegmentsare
shared among the number of logical ports defined by the static NR_LID
configuration. The buffer segments do not have to be equally shared among
the LIDs. One buffer segment corresponds to a data burst to be forwarded to
the SPI-4 egress interface.
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相关代理商/技术参数 |
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| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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