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| 型号： | IDT88P8341BHI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 68/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHI |
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70
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
I_FORCE_TRAIN
The I_FORCE_TRAIN field is used to force continu-
ous training on the SPI-4 ingress status interface.
0=Normal status channel operation
1=Force continuous training on the SPI-4 ingress status interface
I_ERR_INS
The I_ERR_INS field is used to insert the number of DIP-
2errorsontheSPI-4ingressstatusinterfaceprogrammedintotheI_DIP_NUM
field. After the DIP-2 errors are inserted, the I_ERR_INS field will clear itself.
0=Normal status channel operation
1= Insert DIP-2 errors on the SPI-4 ingress status interface
I_DIP_NUM
The I_DIP_NUM field is used to create the number of DIP-2 errors
programmed into the I_DIP_NUM field on the SPI-4 egress status interface..
SPI-4 ingress DIP-4 error counter (Block_base
0x0300 + Register_offset 0x10)
TABLE 98 - SPI-4 INGRESS DIP-4 ERROR
COUNTER (REGISTER_OFFSET 0x10)
Field
Bits
Length
Initial Value
DIP_4
15:0
16
0
The SPI-4 ingress DIP-4 error counter is addressed from Block_base
0x0300 + Register_offset 0x10. The SPI-4 ingress DIP-4 error counter has
readaccess,andautomaticallyclearsitselfafteraread.TheSPI-4ingressDIP-
4 error counter is used in port diagnostics to verify the integrity of the SPI-4
ingress data path.
DIP_4 The DIP_4 field is used to read the number of DIP-4 errors seen on
the SPI-4 egress status interface. The DIP_4 field saturates at the value
0xFFFF, and is automatically cleared after reading to re-start DIP-4 error
counteraccumulation.
SPI-4 ingress bit alignment control register
(Block_base 0x0300 + Register_offset 0x11)
TABLE 99 - SPI-4 INGRESS BIT ALIGNMENT
CONTROL REGISTER (REGISTER_OFFSET 0x11)
Field
Bits
Length
Initial Value
FORCE
0
1
0
TheSPI-4ingressbitalignmentcontrolregisterisaddressedfromBlock_base
0x0300+Register_offset0x11.TheSPI-4ingressbitalignmentcontrolregister
has read and write access. The SPI-4 ingress bit alignment control register is
used to overrule the automatically selected bit phase alignments and go to
manualmode.Inmanualmode,thePHASE_ASSIGNfield[Block_base0x0800
+ Register_offset 0x0c – 0x1F] now defines the selected phase.
FORCE
TheFORCEfieldisusedtomanuallyaligntheSPI-4ingressdata.
0=Normal bit alignment operation
1= Force to manual bit alignment mode on SPI-4 ingress data using
the PHASE_ASSIGN field.
SPI-4 ingress start up training threshold register
(Block_base 0x0300 + Register_offset 0x12)
TABLE 101 - SPI-4 EGRESS LID TO LP MAP
(256 ENTRIES)
Field
Bits
Length
Initial Value
LP
7:0
8
0x00
EN
8
1
0b0
There are 64 entries in the SPI-4 egress LID to LP map for the SPI-4 ingress
interface. The entries are at Block_base 0x0400 + LID. For example, LID 0x00
is at Block_base 0x0400 + 0x00. A SPI-4 egress LID to LP map has read and
write access. A SPI-4 egress LID to LP map is used to map a logical identifier
used internally to a SPI-4 egress logical port.
Data for an inactive LP having an entry in the calendar is forwarded to
LID0. Therefore all the LPs that have entries in the calendar tables should be
enabled.
LP The LP programmed is associated to the LID with the same number as
the register address. Eight bits support the 256 possible LPs on the SPI-4
physical interface. Only 64 LPs are supported in the IDT88P8341 device.
EN The EN bit is used to enable or disable the connection of a LID to an LP.
0=LP is disabled
1=LP is enabled
9.4.6 Common module block base 0x0500 registers
SPI-4 egress calendar_0 (Block_base 0x0500 +
Register_offset 0x00 – 0xFF)
TABLE 102 - SPI-4 EGRESS CALENDAR_0
(256 LOCATIONS)
Field
Bits
Length
Initial Value
LP
7:0
8
0xFF
The SPI-4 egress calendar_0 is at Block_base 0x0500 and has read and
write access. When the SPI-4 egress calendar_0 is selected, calendar_0 is
in use. There are 256 entries in the SPI-4 egress calendar_0 to schedule the
updating of the FIFO status channel LPs to the attached device. If less than the
maximum 256 LPs are needed on the SPI-4 interface, the calendar entries
should be used for scheduling more frequent status updated for higher-speed
LPs. The value of time-critical LPs must appear multiple times in the table. For
example, a multi-PHY SPI-4 could have OC-48 channels appear in the
calendar at four times the rate of OC-12 channels, since the higher data rate
of the OC-48 channels would benefit from more frequent FIFO status channel
updates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 and
the attached devices must have identical calendars.
The SPI-4 ingress start up training threshold register is addressed from
Block_base0x0300+Register_offset0x12.TheSPI-4ingressstartuptraining
thresholdregisterhasreadandwriteaccess.TheSPI-4ingressstartuptraining
thresholdregisterisusedtosetthenumberofconsecutivetrainingpatternsthat
will lead to OUT_OF_SYNCH on the SPI-4 ingress data. If the STRT_TRAIN
field is set to zero, then the OUT_OF_SYNCH feature is disabled.
STRT_TRAIN
The STRT_TRAIN field is used to set the number of
consecutive training patterns that will lead to OUT_OF_SYNCH on the SPI-4
ingress data interface.
9.4.5 Common module block base 0x0400 registers
SPI-4 egress LID to LP map (Block_base 0x0400 +
Register_offset 0x00 - 0x3F)
TABLE 100 - SPI-4 INGRESS START UP TRAINING
THRESHOLDREGISTER(REGISTER_OFFSET0x12)
Field
Bits
Length
Initial Value
STRT_TRAIN
7:0
8
0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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