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| 型号： | IDT88P8344BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8344BHGI |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-4 egress status channel
Status channel bit alignment
Thebitalignmentalgorithmforthestatuschannelisthesameaswasdescribed
for the data channel.
Validate
IN_SYNCH
A
B
A= a number of consecutive error free DIP-2s received
B= a number of consecutive DIP-2 errors, in training,
port disabled, or reset
HUNT
C
D
6370 drw30
Figure 9. SPI-4 egress status state diagram
The status channel frame module has 3 states: HUNT, VALIDATE and
IN_SYNCH.
In the HUNT state, the status channel frame module searches for status
frame, status clear and status freeze.
In the VALIDATE state, the status channel frame module checks DIP-2.
IntheIN_SYNCHstate,thestatuschannelframemodulechecksDIP-2,and
updatesstatus.
HUNT state
In the HUNT state, per Link status is fixed to ‘satisfied’.
InHUNTstate,thePFPsearchesframecontinuously. Ittransitionstothe
VALIDATE state if a single valid frame is found accompanied by a single valid
training pattern. A frame is considered to be found if : 1) only one frame word
is at the beginning of a frame, 2) the calendar selection word, if enabled, is
matched, and 3) the DIP-2 calculation matched the received DIP-2.
VALIDATE state
In the validate state, based on the frame found while in the HUNT state,
the DIP-2 is checked.
If a single DIP-2 error is found, transition to the HUNT state.
After a number of consecutive DIP-2 calculations proves to be error free,
transitiontotheIN_SYNCHstate.ThenumberisdefinedbytheE_INSYNC_THR
field in Table 104-SPI-4 egress configuration register_0 (Block_base 0x0700
+ Register_offset 0x00).
In the validate state, the training pattern is not checked.
IN_SYNCH state
In the IN_SYNCH state, training frame and status frame are checked.
DIP-2 is checked for status frame. Each mismatched DIP-2 will generate a
DIP-2 error event, each event will be captured and counted.
After a number of consecutive DIP-2 errors, transition to the HUNT state.
(ClearstatusinHUNTmode).ThenumberisdefinedbytheE_OUTSYNC_THR
field in Table 104-SPI-4 egress configuration register_0 (Block_base 0x0700
+ Register_offset 0x00).
The reception of twelve consecutive training patterns forces a transition to
HUNT mode. If less than twelve consecutive training patterns are received,
synch will not be lost, and status frame starts at the end of training.
Twelve consecutive ‘11’ patterns force a transition to the HUNT state.
Status updating occurs without waiting for the end of a status frame.
LVTTL or LVDS status channel option
TheLVDS_STApinselectstheinterfacetype.AlogichighenablestheLVDS
status interface. A logic low enables the LVTTL status interface.
Data channel
Data transfer and training
At any cycle, the contents on the interface can be one of the following:
Controlword:Payloadcontrolword,oridlecontrolwordortrainingcontrol
word.
Data word: Payload data word or training data word.
In the HUNT or the VALIDATE state, the training pattern is sent.
In the IN_SYNCH state, data from is taken from the buffer segments and
egressed to the SPI-4 interface. The switch between data burst, IDLE, and
training must obey the following rules:
Send IDLE if no data to transmit
SOP must not occur less than 8 cycles apart.
periodictrainingaftercurrenttransferfinished
Payload control word generation:
Bit 15, Control word type=1
Bit [14:13] EOPS per [see Glossary: SPI-4]. If an error tag is in the
descriptor, abort.
Bit [12] SOP refer to [see Glossary: SPI-4]
EightBitAddress.MappingtabledefinedinTable101,SPI-4egressLID
to LP map (256 entries)
DIP-4 bit refer to [see Glossary]
Payload data word
Bit order refer to [see Glossary: SPI-4]
If only one byte is valid, 8 LSB (B7 to B0) is set to 0x00.
No status channel option
OncetheNOSTATbitisset,thestatuschannelisignored.RefertoTable104,
SPI-4 egress configuration register_0 (register_offset 0x00).
Status in default value.
No DIP error check.
No status updating, the received status fixed to STARVING.
Data channel works same as in IN_SYNCH state.
Status Channel Frame synchronization
Status channel de-skew
TheLVDSstatuschanneldeskewusesthesamealgorithmastheasthedata
channel.
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相关代理商/技术参数 |
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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