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参数资料
型号： IDT88P8344BHGI
厂商： IDT, Integrated Device Technology Inc
文件页数： 69/98页
文件大小： 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
标准包装： 24
系列： *
其它名称： 88P8344BHGI
71
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-4 ingress calendar configuration register
(Block_base 0x0300 + Register_offset 0x04 - 0x05)
TABLE 93 - SPI-4 INGRESS CALENDAR CONFIGU-
RATION REGISTER (0x04 to 0x05)
Field
Bits
Length
Initial Value
I_CAL_M
7:0
8
0
I_CAL_LEN
13:8
6
0x01
The SPI-4 ingress calendar configuration registers are at Block_base
0x0300 and have read and write access. The Register_offset for calendar_0
is 0x04. The Register_offset for calendar_1 is 0x05.
ThebitfieldsofaSPI-4ingresscalendarconfigurationregisteraredescribed.
Some devices have a fixed calendar length and a fixed calendar M, while
the Bridgeport calendar length has to be multiply of 4, and the calendar M is
programmable. Therefore, the user may need to add an FPGA between the
Bridgeport & the adjacent device SPI-4 status signals.
I_CAL_M
TheI_CAL_Mvalueprogrammeddefinesthenumberoftimes
the calendar sequence is repeated before a DIP-2 parity and “1 1” framing
words are inserted. The actual calendar_M value used is one more than the
value programmed into the I_CAL_M field.
I_CAL_LEN
TheI_CAL_LENvalueprogrammeddefinesthelengthof
the SPI-4 ingress calendar. The actual length of the calendar is four times the
valueofonemorethantheI_CAL_LENfield:(I_CAL_LEN+1)*4.Forexample,
if the I_CAL_LEN field is programmed to 0x04, the actual value used is 0x14.
The calendar length must be at least as large as the number of active SPI-4
ingress LPs.
SPI-4 ingress watermark register (Block_base
0x0300 + Register_offset 0x06)
SPI-4 ingress fill level register (Block_base 0x0300
+ Register_offset 0x07-0x0A)
Thereisone SPI-4ingressfilllevelregisterperSPI-3interfaceatBlock_base
0x0300. Each register has read-only access.
The SPI-4 ingress fill level register for PFP A is at Block_base 0x0300 +
Register_offset0x07.
The SPI-4 ingress fill level register for PFP B is at Block_base 0x0300 +
Register_offset0x08.
The SPI-4 ingress fill level register for PFP C is at Block_base 0x0300 +
Register_offset0x09.
The SPI-4 ingress fill level register for PFP D is at Block_base 0x0300 +
Register_offset0x0A.
The bit field of a SPI-4 ingress fill level register is described.
TABLE 94 – SPI-4 INGRESS WATERMARK REGIS-
TER (REGISTER_OFFSET 0x06)
Field
Bits
Length Initial Value
Function
WATERMARK
4:0
5
0x0D
Watermark for PFP A
reserved
7:5
3
0
WATERMARK
12:6
5
0x0D
Watermark for PFP B
reserved
15:13
3
0
WATERMARK
20:16
5
0x0D
Watermark for PFP C
reserved
23:21
3
0
WATERMARK
28:24
5
0x0D
Watermark for PFP D
reserved
31:29
3
0
SPI-4ingressWatermarkRegisterisatBlock_base0x0300,Register_offset
0x06.TheSPI-4ingressWatermarkRegisterhasreadandwriteaccess.ASPI-
4 interface can be set to a Watermark Value per PFP. 0x1F is the highest
watermark that can be set, meaning all ingress buffers will be full before
backpressure will be initiated on a SPI-4 ingress interface PFP. A WATER-
MARKfieldvalueof0x0Fisusedtosetawatermarkforahalf-fullingressbuffer
before tripping backpressure. The units of WATERMARK are one-thirty-
secondoftheavailableingressbufferingperunit.Eachunitisequalto128bytes.
TABLE 95 - SPI-4 INGRESS FILL LEVEL REGISTER
(0x07 to 0x0A)
Field
Bits
Length
Initial Value
FILL_CUR
5:0
6
0x0
TABLE 96 - SPI-4 INGRESS MAX FILL LEVEL
REGISTER (0x0B to 0x0E)
Field
Bits
Length
Initial Value
FILL_MAX
5:0
6
0x00
There are four SPI-4 ingress max fill level registers, one per SPI-3 interface,
atBlock_base0x0300.Eachregisterhasread-onlyaccess,andisclearedafter
reading. The value 0x20 is the highest filling level, meaning all ingress buffers
on a PFP had been full at some time since the last read of the FILL_MAX field.
TheunitsofFILL_MAXareone-thirty-secondoftheavailableingressbuffering
per PFP. Each unit is equal to 128 bytes.
The SPI-4 ingress max fill level register for PFP A is at Block_base 0x0300
+ Register_offset 0x0B.
The SPI-4 ingress max fill level register for PFP B is at Block_base 0x0300
+ Register_offset 0x0C.
The SPI-4 ingress max fill level register for PFP C is at Block_base 0x0300
+ Register_offset 0x0D.
The SPI-4 ingress max fill level register for PFP D is at Block_base 0x0300
+ Register_offset 0x0E.
The bit field of a SPI-4 ingress max fill level register is described.
FILL_MAX MaximumSPI-4ingressbufferfilllevelsincethelastreadofthe
SPI-4 ingress max fill level register.
SPI-4 ingress diagnostics register (Block_base
0x0300 + Register_offset 0x0F)
TABLE 97 - SPI-4 INGRESS DIAGNOSTICS REGIS-
TER (REGISTER_OFFSET 0x0F)
Field
Bits
Length
Initial Value
I_FORCE_TRAIN
0
1
0
I_ERR_INS
1
0
I_DIP_NUM
5:2
4
0
FILL_CUR
Current SPI-4 ingress buffer fill level. Since this is a real-time
register, the value read from it will change rapidly and is used for internal
diagnosticsonly.
SPI-4 ingress max fill level register (Block_base
0x0300 + Register_offset 0x0B to 0x0E)
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