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| 型号： | IDT88P8344BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 71/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8344BHGI |
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73
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
updating of the FIFO status channel LPs to the attached device. If less than the
maximum 256 LPs are needed on the SPI-4 interface, the calendar entries
should be used for scheduling more frequent status updated for higher-speed
LPs. The value of time-critical LPs must appear multiple times in the table. For
example, a multi-PHY SPI-4 could have OC-48 channels appear in the
calendar at four times the rate of OC-12 channels, since the higher data rate of
the OC-48 channels would benefit from more frequent FIFO status channel
updates. The LP field values range from 0x00 to 0xFF. The IDT88P8344 and
the attached devices must have identical calendars.
LP
The LP value programmed schedules a status channel update
according to the calendar sequence.
9.4.7 Common module block base 0x0600 registers
SPI-4 egress calendar_1 (Block_base 0x0600)
TABLE 103 - SPI-4 EGRESS CALENDAR_1
(256 LOCATIONS)
Field
Bits
Length
Initial Value
LP
7:0
8
0xFF
The SPI-4 egress calendar_1 is at Block_base 0x0600 and had read and
write access. When the SPI-4 egress calendar_1 is selected, calendar_1 is in
use. There are 256 entries in the SPI-4 egress calendar_1 to schedule the
updating of the FIFO status channel LPs to the attached device. If less than the
maximum 256 LPs are needed on the SPI-4 interface, the calendar entries
should be used for scheduling more frequent status updated for higher-speed
LPs. The value of time-critical LPs must appear multiple times in the table. For
example, a multi-PHY SPI-4 could have OC-48 channels appear in the
calendar at four times the rate of OC-12 channels, since the higher data rate of
the OC-48 channels would benefit from more frequent FIFO status channel
updates. The LP field values range from 0x00 to 0xFF. The IDT88P8344 and
the attached devices must have identical calendars.
LP
The LP value programmed schedules a status channel update
according to the calendar sequence.
9.4.8 Common module block base 0x0700 registers
SPI-4 egress configuration register_0 (Block_base
0x0700 + Register_offset 0x00)
TheSPI-4egressconfigurationregister_0isatBlock_base0x0700andhas
read and write access.
The SPI-4 egress configuration register_0 is used to set the state of the SPI-
4egressinterface.ThebitfieldsoftheSPI-4egressconfigurationregister_0are
described.
TABLE 104 – SPI-4 EGRESS CONFIGURATION
REGISTER_0 (REGISTER_OFFSET 0x00)
Field
Bits
Length
Initial Value
Reserved
2:0
3
0
E_CLK_EDGE
3
1
0
E_DSC
4
1
0
E_INSYNC_THR
9:5
5
0x1F
E_OUTSYNC_THR
13:10
4
0xF
E_CSW_EN
14
1
0
Reserved
15
1
0
E_LOW
16
1
NOSTAT
17
1
0
E_CLK_EDGE TheSPI-4egressclockactiveclockedgeisselectedusing
the E_CLK_EDGE field.
0=SPI-4 egress clock uses the rising clock edge
1=SPI-4 egress clock uses the falling clock edge
E_DSC
The E_DSC bit enables or disables de-skewing of the SPI-4
egress data lines.
0=Data de-skewing is disabled
1=Data de-skewing is enabled (recommended)
E_INSYNC_THR
The SPI-4 egress DIP-2 in-synchronization thresh-
old is controlled using the E_INSYNC_THR field. It is recommended to use the
initial value.
E_OUTSYNC_THR
The SPI-4 egress DIP-2 out-of-synchronization
threshold is controlled using the E_OUTSYNC_THR field. It is recommended
to use the initial value.
E_CSW_EN
The ingress calendar switch enable bit is used to enable
the switching of the active calendars following the reception of the calendar
selectionwordonthestatuschannel.Itisrecommendedtousetheinitialvalue.
0=Egress calendar switch is disabled. Only SPI-4 egress calen-
dar_0 is used.
1=Egress calendar switch is enabled. Calendar_0 or calendar_1
will be used.
E_LOW
The E_LOW field selects the SPI-4 egress clock frequency
range.
0=SPI-4 egress clock is greater than or equal to 200 MHz
1=SPI-4 egress clock is less than 200 MHz
NOSTAT
The NOSTAT bit enables the no status channel option. Once
NOSTATisset,thestatuschannelisignored.ThereisnoDIP-2errorchecking,
and no status channel updating. The received status is fixed to starving. The
data channel is put into the IN_SYNCH state.
0=Normal status channel operation
1=No status channel option is selected
SPI-4 egress configuration register_1 (Block_base
0x0700 + Register_offset 0x01)
TABLE 105 - SPI-4 EGRESS CONFIGURATION
REGISTER_1 (REGISTER_OFFSET 0x01)
Field
Bits
Length
Initial Value
DATA_MAX_T
23:0
24
0
ALPHA
31:24
8
0
TheSPI-4egressconfigurationregister_1isatBlock_base0x0700andhas
read and write access.
The SPI-4 egress configuration register_1 is used to set the state of the SPI-
4 egress FIFO status path interface. The bit fields of the SPI-4 egress
configuration register_1 are described.
DATA_MAX_T
The SPI-4 egress DATA_MAX_T field is the maximum
timeintervalbetweenschedulingoftrainingsequencesontheegressdatapath
interface. The purpose of the data training interval is to allow the de-skewing
of plus or minus one bit time on the egress data interface if needed. The time is
set for the DATA_MAX_T field multiplied by 128 cycles.
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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