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| 型号： | IDT88P8344BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 30/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8344BHGI |
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36
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
4.4.3 Microprocessor interface to SPI-4 egress
datapath
PacketscanbeinsertedintotheSPI-3-4datapathbythemicroprocessor.The
followingis adescriptionofthepathtakenbyaburstofdatathroughthedevice.
Data and control information are written to the insert buffer through the
microprocessorinterface.Thedataavailablebitisset.Dataisstoredintheinsert
buffer along with the LP address, LID, error information, SOP, and EOP. Data
is stored in per-LID allocated buffer segments. The Table 36-SPI-3 data insert
controlregisterisconsulted,anddeterminestosendthisLIDtotheSPI-4egress
port. The SPI-4 Packet Fragment Processor chooses the next LP. Data is sent
to the SPI-4 egress buffer along with the SPI-4 LP address, error information,
SOP, and EOP. Data is transmitted in bursts over the SPI-4 egress interface.
The microprocessor needs to write data into a dedicated buffer to insert a
packet burst. Refer to Figure 26, Microprocessor data insert bufferfor the data
formatinthebuffer.ThemicroprocessormustverifytheDATA_AVAILABLEflag
in the SPI-4 insert control register and waits until the flag is cleared. The
microprocessorspecifiestheEOP,SOP,ERROR,LIDandLENGTHfieldsand
writesupto256bytesofpacketfragmentburstintotheinsertbuffer.Thepacket
burst insert buffer is accessed through the Table 34, SPI-4 data insert register
(register_offsets 0x03, 0x0B, 0x13, 0x1B) SPI-4 data insert register. The
microprocessorhandsovercontrolofthebuffersettingtheDATA_AVAILABLE
flagintheSPI-4insertcontrolregister. ASPI4_insert_emptyeventisgenerated
whentheDATA_AVAILABLEflagiscleared.Theeventisdirectedtowardsthe
interruptmodule.
Figure 26. Microprocessor data insert buffer
6370 drw28
flags
length
data[1]
data[2]
data[255]
lid
data[0]
SOP
EA
ED
PAR
EOP
not used
EA
ED
PAR
data parity error
address parity error
packet error
70
inser
tsequence
t
t+1
t+258
e
xtr
act
sequence
t
t+1
t+258
Figure 27. Microprocessor data insert interface to SPI-4 egress datapath
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
Interface
Bloc
k
Chip Counters Memory
Interface
Bloc
k
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw18
The diagram below shows the datapath through the device from the
microprocessor data insert interface to the SPI-4 egress interface.
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相关代理商/技术参数 |
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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