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| 型号： | IDT88P8344BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 20/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8344BHGI |
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27
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-4 egress data bursts
The PFP produces fragments of up to N*16 bytes. N is defined by the
MAX_BURST_HorMAX_BURST_SparameterassociatedwitheachLID.For
a high priority (starving) LID the MAX_BURST_S parameter is used. For a low
priority (hungry) LID the MAX_BURST_H parameter is used. The PFP may
not fill the buffers to the level granted when a new segment needs to be used
intheSPI3-4buffermemoryorwhenthelastfragmentofapacketiscopiedinto
thebuffer.TheinformationreceivedovertheFIFOstatuschannelisinterpreted
as status or credit information as selected by the CREDIT_EN flag in Table 78,
SPI-3 to SPI-4 flow control register (0x01). If the status mode is used, data will
be egressed until the status is changed. If the credit mode is used, the SPI-4
egresswillissueonlyonecredit’sworthdataburstandthenwaitforanothercredit
from the status channel before issuing another LID burst.
SPI-4 egress FIFO status channel updates
The SPI-4 egress FIFO Status Channel Module continuously verifies the
status information for the LIDs associated to SPI-4 logical ports. The PFP
searchesandselectsaLID,fetchestheassociatedinformationandqueuesdata
to the SPI-4 egress. The obsolete buffer segment is returned to the free buffer
segment pool (unless the repeat test feature is enabled). Searching the LID to
beservedisperformedforbothahighpriorityandalowpriorityLID.Thepriority
is defined by the status received from the SPI-4 egress module.
SPI-3 ingress logical port mapping
Each of the four SPI-3 interfaces has an associated SPI-3 ingress LP to LID
map, (See Table 49) for the purpose of directing the packet fragments from its
SPI-3ingresstoitsassociatedSPI-3ingressmainmemorybuffersegmentpool.
The SPI-3 LID map has 256 entries, one per SPI-3 LP, but only 64 LPs are
supported on any SPI-3 interface at any one time. Each SPI-3 interface has
an enable bit, as well as the ability to reverse the bit ordering of the interface.
The packet fragment length is associated with a SPI-3 interface. The allowed
range is 0 to 255 bytes per packet fragment. The last fragment of a packet can
be shorter than the programmed fragment size. Each SPI-3 port can be
independently set for either Link or PHY mode of operation.
SPI-3 ingress LID associated control
EachLIDonaSPI-3interfacehastheabilitytobeprogrammedforminimum
and maximum packet length. The minimum packet length can be set from 0 to
255bytesinonebyteincrements.Themaximumpacketlengthcanbesetfrom
0to16,383bytesinonebyteincrements.EachLIDcanbeenabledanddisabled
independently.
Figure 14. SPI-3 ingress LP to LID map
6370 drwXC
LID
BRV
EN
256 LPs
[LP] = LID | EN | BRV
LID: Logical Identifier
EN: LID Enable
BRV: Bit Reversal
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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