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参数资料
| 型号： | IDT88P8344BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 59/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8344BHGI |
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62
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Non LID associated interrupt indication register
(Block_base 0x0C00 + Register_offset 0x0C)
TABLE 62 - NON LID ASSOCIATED INTERRUPT
INDICATIONREGISTER(REGISTER_OFFSET
0x0C)
Field
Bits
Length
Initial Value
SPI4_LOCK_UN
0
1
0b0
SPI3_LOCK_UN
1
0b0
SPI3_ICLK_UN
2
1
0b0
SPI3_ECLK_UN
3
1
0b0
SPI3_FLUSH
4
1
0b0
Reserved
31:5
27
0x0
The Non LID associated interrupt indication register is at Block_Base
0x0C00.TheNonLIDinterruptindicationregisterisusedtodeterminethestatus
of SPI-3 and SPI-4 port interrupts. The Non LID associated interrupt indication
register is read and subsequently a “1” is written to acknowledge individual
interrupts in this register. An interrupt is generated when enabled by the
corresponding enable flag in the Non LID associated interrupt indication
register.ThebitfieldsintheNonLIDassociatedinterruptindicationregisterare
described.
SPI4_LOCK_UN TheSPI-4interfacecancreateaneventindicatingthat
the SPI-4 ingress has dropped data due the unavailability of ingress buffering.
0=No operation
1=The SPI-4 interface has dropped data due the
unavailability of ingress buffering.
SPI3_LOCK_UN A SPI-3 interface can create an event indicating that a
SPI-3 ingress has dropped data due the unavailability of ingress buffering.
0=No operation
1=A SPI-3 interface has dropped data due the
unavailability of ingress buffering.
SPI3_ICLK_UN
A SPI-3 interface can create an event indicating that a
SPI-3 ingress clock has failed. No transitions were detected on a SPI-3 ingress
clock (I_FCLK)
0=No operation
1=A SPI-3 ingress clock has failed.
SPI3_ECLK_UN
A SPI-3 interface can create an event indicating that a
SPI-3 egress clock has failed. No transitions were detected on a SPI-3 egress
clock (E_FCLK)
0=No operation
1=A SPI-3 egress clock has failed.
SPI3_FLUSH
A SPI-3 interface can create an event indicating that a
SPI-3 buffer has been flushed and data has been lost. A buffer is flushed if an
addressparityerrorisdetected,orifaningressbufferisnotavailableatthetime
it is requested.
0=No operation
1=A SPI-3 buffer has been flushed.
Non LID associated interrupt enable register
(Block_base 0x0C00 + Register_offset 0x0D)
TABLE 63 - NON LID ASSOCIATED INTERRUPT
ENABLEREGISTER(REGISTER_OFFSET0x0D)
Field
Bits
Length
Initial Value
SPI4_LOCK_UN
0
1
0b0
SPI3_LOCK_UN
1
0b0
SPI3_ICLK_UN
2
1
0b0
SPI3_ECLK_UN
3
1
0b0
SPI3_FLUSH
4
1
0b0
Reserved
31:5
27
0x0000
The Non LID associated interrupt enable register is at Block_Base 0x0C00
+ Register_offset 0x0D. The Non LID associated interrupt enable register is
used to mask the status of SPI-3 and SPI-4 port interrupts in the Non LID
associatedinterruptindicationregister.TheNonLIDassociatedinterruptenable
register has read and write access. The bit fields in the Non LID associated
interrupt enable register are active “1” interrupt enables for the corresponding
bit fields in the Non LID associated interrupt indication register.
LID associated interrupt indication register
(Block_base 0x0C00 + Register_offset 0x0E)
TABLE 64 - LID ASSOCIATED INTERRUPT INDICA-
TION REGISTER (REGISTER_OFFSET 0x0E)
Field
Bits
Length
Initial Value
EVENT_TYPE
5:0
6
0x00
Reserved
31:6
26
0x0
The LID associated interrupt indication register is at Block_Base 0x0C00 +
Register_offset 0x0E. The LID associated interrupt indication register is used
to determine the EVENT_TYPE of SPI-3 and SPI-4 interrupts. The
EVENT_TYPE coding is given in the Table 66 - Non critical LID associated
capture table (0x10-0x15). The LID associated interrupt indication register is
read and subsequently a 0xFF must be written for interrupt acknowledge. An
EVENT_TYPE interrupt is generated when enabled by the EVENT_TYPE
enable flag in the LID associated interrupt enable register.
LID associated interrupt enable register
(Block_base 0x0C00 + Register_offset 0x0F)
TABLE 65 - LID ASSOCIATED INTERRUPT ENABLE
REGISTER(REGISTER_OFFSET0x0F)
Field
Bits
Length
Initial Value
EVENT_TYPE
5:0
6
0x00
Reserved
31:6
26
0x0
The LID associated interrupt enable register is at Block_Base 0x0C00 +
Register_offset 0x0F. The LID associated interrupt enable register is used to
mask the EVENT_TYPE of SPI-3 and SPI-4 per-LID interrupts. The LID
associated interrupt enable register has read and write access.
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相关代理商/技术参数 |
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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