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参数资料
型号： IDT88P8344BHGI
厂商： IDT, Integrated Device Technology Inc
文件页数： 68/98页
文件大小： 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
标准包装： 24
系列： *
其它名称： 88P8344BHGI
70
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-4_EN The SPI-4 ingress path is enabled using this field. The SPI-4
pathisdisabledduringresetandwhileconfiguringtheport,andthenisenabled
for normal use.
0=SPI-4 ingress is disabled
1= SPI-4 ingress is enabled
I_CLK_EDGE
The SPI-4 ingress LVTTL status clock active clock edge
is selected using the I_CLK_EDGE field.
0=SPI-4 ingress LVTTL status clock uses the rising edge
1= SPI-4 ingress LVTTL status clock uses the falling edge
I_DSC
The I_DSC bit is used to protect against a random data error
during de-skew.
0= One de-skew result is needed for data de-skew
1= Two consecutive de-skew results are needed for data de-skew
(recommendedsetting)
I_INSYNC_THR
The SPI-4 ingress DIP-4 in synchronization threshold
iscontrolledusingtheI_INSYNC_THRfield.Itisrecommendedtousetheinitial
value.
I_OUTSYNC_THR The SPI-4 ingress DIP-4 out-of synchronization
thresholdiscontrolledusingtheI_OUTSYNC_THRfield.Itisrecommendedto
use the initial value.
I_CSW_EN
The ingress calendar switch enable bit is used to enable the
switching of the active calendars. It is recommended to use the initial value.
0=Ingresscalendarswitchdisabled.OnlySPI-4ingresscalendar_0
is used.
1=Ingress calendar switch enabled. Calendar_0 or calendar_1 can
be used.
CAL_SEL
The calendar select bit selects between SPI-4 ingress
calendar_0 and SPI-4 ingress calendar_1. The CAL_SEL bit is only valid if the
I_CSW_EN bit is set to a logic one.
0=SPI-4 ingress calendar_0 is selected
1=SPI-4ingresscalendar_1isselectediftheI_CSW_ENbitissetto
a logic one
I_LOW
TheI_LOWfieldselectstheSPI-4ingressclockfrequencyrange.
0=SPI-4 ingress clock is greater than or equal to 200 MHz
1=SPI-4 ingress clock is less than 200 MHz
SPI-4 ingress status configuration register
(Block_base 0x0300 + Register_offset 0x01)
FIFO_MAX_T
TheSPI-4ingressFIFO_MAX_Tfieldisthemaximumtime
interval between scheduling of training sequences on the FIFO status path
interface. The units are the number of times the calendar is sent before
scheduling the training sequence.
ALPHA_FIFO
The SPI-4 ingress ALPHA_FIFO field is the number of
repetitions of the status training sequence that must be scheduled every
FIFO_MAX_T cycles. The value for alpha used is actually one more than the
ALPHA_FIFO value programmed into the ALPHA_FIFO field.
SPI-4 ingress status register (Block_base 0x0300 +
Register_offset 0x02)
TABLE 90 - SPI-4 INGRESS STATUS CONFIGURA-
TION REGISTER (REGISTER_OFFSET 0x01)
Field
Bits
Length
Initial Value
FIFO_MAX_T
23:0
24
0
ALPHA_FIFO
31:24
8
0
TheSPI-4ingressstatusconfigurationregisterisatBlock_base0x0300and
has read and write access.
The SPI-4 ingress status configuration register is used to set the state of the
SPI-4ingressFIFOstatuspathinterface.ThebitfieldsoftheSPI-4ingressstatus
configuration register are described.
TABLE 91 - SPI-4 INGRESS STATUS REGISTER
(REGISTER_OFFSET 0x02)
Field
Bits
Length
Initial Value
I_SYNCH
0
1
0
I_DSK_OOR
1
0
DCLK_AV
2
1
0
TheSPI-4ingressstatusregisterisatBlock_base0x0300andhasread-only
access.
The SPI-4 ingress status register is used to set the state of the SPI-4 ingress
synchronization.
The bit fields of the SPI-4 ingress status register are described.
I_SYNCH The SPI-4 ingress I_SYNCH field describes the synchroniza-
tion state of the SPI-4 ingress data path.
0=SPI-4 ingress data path is out of synchronization
1=SPI-4 ingress data path is in synchronization
I_DSK_OOR TheSPI-4ingressI_DSK_OORfield describesthede-skew
state of the SPI-4 ingress data path.
0=SPI-4 ingress data path de-skew is within range
1= SPI-4 ingress data path de-skew is out of range
DCLK_AV
The SPI-4 ingress DCLK_AV field describes the availability
state of the SPI-4 ingress clock.
0=SPI-4 ingress clock is not available
1= SPI-4 ingress clock is available
SPI-4 ingress inactive transfer port (Block_base
0x0300 + Register_offset 0x03)
TABLE 92 - SPI-4 INGRESS INACTIVE TRANSFER
PORT (REGISTER_OFFSET 0x03)
Field
Bits
Length
Initial Value
INACT_LP
7:0
8
0
The SPI-4 ingress inactive transfer port is at Block_base 0x0300 and has
read-only access.
The SPI-4 ingress inactive transfer port INACT_LP field is used to monitor
the LP associated with the latest inactive transfer. The INACT_LP field can
change at any time and is used for diagnostics only.
INACT_LP
TheSPI-4ingressINACT_LPfieldcontainsthenumericvalue
oftheLPassociatedwiththelastinactiveLPtransfer,usedfordiagnosticsonly.
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