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| 型号： | IDT88P8344BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 48/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8344BHGI |
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52
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Software reset
The SPI-4 Status Register (0x22 in the direct accessed space) has read
access, and interrupt status fields are cleared by a microprocessor write cycle,
where a logical one must be written to clear the field(s) targeted.
The SPI-4 Status Register is a secondary interrupt status register and can
only be active if the SPI-4 field is active in the Primary Interrupt Status Register
(Direct 0x2C).
I_DIP_ERR_I
SPI-4 ingress DIP-4 error interrupt indication.
0=No errors
1=One or more DIP-4 errors have been registered on the SPI-4 ingress
I_SYNCH_I
SPI-4 ingress data path has transitioned from out of
synchronization to in synchronization condition interrupt indication.
0=No detection, still not in synchronization
1=Transition from out of synchronization to in synchronization, or transition
from in synchronization to out of synchronization
I_BUS_ERR_I SPI-4 ingress bus error interrupt indication.
0=No errors
1=One or more bus errors have been registered on the SPI-4 ingress
SPI4_INACTIVE_TRANSFER_I
SPI-4ingressinactivetransferinter-
ruptindication.
0=Noindication
1=OneormoreinactivetransfershavebeenregisteredontheSPI-4ingress
DCLK_UN_I
SPI-4 ingress data clock has transitioned from available
to an unavailable condition interrupt indication.
0=No detection, I_DCLK is available
1=I_DCLK transitioned from available to an unavailable state
E_DIP_ERR_I
SPI-4 egress DIP-2 error interrupt indication on the SPI-
4 egress status channel.
0=No errors
1=One or more DIP-2 errors have been registered
E_SYNCH_I
SPI-4 egress status channel has transitioned from out of
synchronization to an in synchronization condition interrupt indication.
0=No detection, still not in synchronization
1=Transition from out of synchronization to in synchronization, or transition
from in synchronization to out of synchronization
SCLK_UN_I
SPI-4egressstatusclockhastransitionedfromavailable
to an unavailable condition interrupt indication.
In LVTTL mode the Bridgeport does not detect the SPI-4 egress status clock
(E_SCLK_T). Therefore, for LVTTL mode the software should ignore the
SCLK_UN field in the SPI-4 Status Register.
0=No detection, E_SCLK is available
1=E_SCLK transitioned from available to an unavailable state
SPI-4 enable register (0x23 in the direct accessed
space)
The SPI-4 Enable Register (0x23 in the direct accessed space) has read
andwriteaccess.SPI-4EnableRegisterisusedtobitwiseenabletheinterrupts
in the SPI-4 Status Register.
I_DIP4_ERR_EN SPI-4 ingress DIP-4 error interrupt indication enable.
0=Disable DIP-4 error interrupt
1=Enable DIP-4 error interrupt
Field
Bits
Length
Initial Val
I_DIP4_ERR_EN
0
1
0
I_SYNCH_EN
1
0
I_BUS_ERR_EN
2
1
0
SPI4_INACTIVE_TRANSFER_EN
3
1
0
DCLK_UN_EN
4
1
0
E_DIP_ERR_EN
5
1
0
E_SYNCH_EN
6
1
0
SCLK_UN_EN
7
1
0
TABLE 41 - SPI-4 ENABLE REGISTER (0x23 IN
THEDIRECTACCESSEDSPACE)
Field
Bits
Length
Initial Val
I_DIP_ERR_I
0
1
0
I_SYNCH_I
1
0
I_BUS_ERR_I
2
1
0
SPI4_INACTIVE_TRANSFER_I
3
1
0
DCLK_UN_I
4
1
0
E_DIP_ERR_I
5
1
0
E_SYNCH_I
6
1
0
SCLK_UN_I
7
1
0
TABLE 40 - SPI-4 STATUS REGISTER (0x22 IN THE
DIRECTACCESSEDSPACE)
TABLE 39 - SOFTWARE RESET REGISTER (0x20 in
the direct accessed space)
Field
Bits
Length
Initial Value
SW_RESET
0
1
0
INIT_DONE
1
0
Reserved
7:2
6
0
The software reset bit is writable from the direct accessed memory space.
Writea“1”totheSW_RESETbittoinitiatethesoftwarereset.TheSW_RESET
bit will clear to a “0” after the chip has initialized itself. The INIT_DONE bit is set
toa“1”whentheinitializationfollowingresethascompleted.Thesoftwarereset
is the same as the hardware. The Reserved field must be set to 0.
TheInitialValuecolumninthisdocumentisthevalueoftheregisterafterreset
hascompleted.
SW_RESET SettingtheSW_RESETbitinitiatesasoftwareresetofthechip.
The SW_RESET bit is self-clearing.
0=No operation is performed
1=Initiate a software reset
INIT_DONE Status indication bit following a reset.
0=Chip has not completed initialization following reset
1= Chip has completed initialization following reset
SPI-4 status register (0x22 in the direct accessed
space)
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相关代理商/技术参数 |
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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