
Table of Contents
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
2
IEEE 1149.1-Compliant Boundary Scan Testability................................................................................ 2-31
Device Configuration............................................................................................................................... 2-32
Internal Logic Analyzer Capability (ispTRACY)....................................................................................... 2-32
External Resistor..................................................................................................................................... 2-32
Oscillator ................................................................................................................................................. 2-33
Density Shifting ................................................................................................................................................ 2-33
DC and Switching Characteristics
Absolute Maximum Ratings ............................................................................................................................... 3-1
Recommended Operating Conditions ................................................................................................................ 3-1
Hot Socketing Specifications.............................................................................................................................. 3-1
DC Electrical Characteristics.............................................................................................................................. 3-2
Supply Current (Standby)................................................................................................................................... 3-3
Initialization Supply Current ............................................................................................................................... 3-4
sysIO Recommended Operating Conditions...................................................................................................... 3-5
sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-6
sysIO Differential Electrical Characteristics ....................................................................................................... 3-7
LVDS......................................................................................................................................................... 3-7
Differential HSTL and SSTL...................................................................................................................... 3-8
LVDS25E .................................................................................................................................................. 3-8
BLVDS ...................................................................................................................................................... 3-9
LVPECL .................................................................................................................................................. 3-10
RSDS ...................................................................................................................................................... 3-11
Typical Building Block Function Performance.................................................................................................. 3-12
Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-12
Register-to-Register Performance1 ........................................................................................................ 3-12
Derating Timing Tables .................................................................................................................................... 3-13
LatticeECP/EC External Switching Characteristics.......................................................................................... 3-14
LatticeECP/EC Internal Switching Characteristics ........................................................................................... 3-16
Timing Diagrams .............................................................................................................................................. 3-18
PFU Timing Diagrams............................................................................................................................. 3-18
EBR Memory Timing Diagrams............................................................................................................... 3-19
LatticeECP/EC Family Timing Adders, , ........................................................................................................... 3-21
sysCLOCK PLL Timing .................................................................................................................................... 3-23
LatticeECP/EC sysCONFIG Port Timing Specifications .................................................................................. 3-24
Master Clock ........................................................................................................................................... 3-25
JTAG Port Timing Specifications ..................................................................................................................... 3-29
Switching Test Conditions................................................................................................................................ 3-30
Pinout Information
Signal Descriptions ............................................................................................................................................ 4-1
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-3
Pin Information Summary................................................................................................................................... 4-4
Pin Information Summary (Cont.)....................................................................................................................... 4-5
Power Supply and NC Connections................................................................................................................... 4-6
Power Supply and NC Connections (Cont.)....................................................................................................... 4-7
LFEC1, LFEC3 Logic Signal Connections: 100 TQFP....................................................................................... 4-8
LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP ............................................................... 4-11
LFEC1, LFEC3 Logic Signal Connections: 208 PQFP .................................................................................... 4-14
LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP.................................................................. 4-19
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA ..................................................................... 4-24
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA......................................................... 4-31
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA ......................................... 4-38
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA......................................................... 4-49
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA............................................................... 4-62
Thermal Management ...................................................................................................................................... 4-80