
Lattice Semiconductor
LatticeECP-DSP sysDSP Usage Guide
15-17
property REG_PIPELINE_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_OUTPUT_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_OUTPUT_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_OUTPUT_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_SIGNEDAB_0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_SIGNEDAB_0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_SIGNEDAB_0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_SIGNEDAB_1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_SIGNEDAB_1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_SIGNEDAB_1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property SHIFT_IN_A {“FALSE”, “TRUE”};
property SHIFT_IN_B {“FALSE”, “TRUE”};
property GSR {“ENABLED”,”DISABLED”};
MULT9X9MAC Primitive
MULT9X9MAC(CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3,SIGNEDAB,ADDNSUB,ACCUMS-
LOAD,
A0,A1,A2,A3,A4,A5,A6,A7,A8,
B0,B1,B2,B3,B4,B5,B6,B7,B8,
SRIA0,SRIA1,SRIA2,SRIA3,SRIA4,SRIA5,SRIA6,SRIA7,SRIA8,
SRIB0,SRIB1,SRIB2,SRIB3,SRIB4,SRIB5,SRIB6,SRIB7,SRIB8,
SROA0,SROA1,SROA2,SROA3,SROA4,SROA5,SROA6,SROA7,SROA8,
SROB0,SROB1,SROB2,SROB3,SROB4,SROB5,SROB6,SROB7,SROB8,
ACCUM0,ACCUM1,ACCUM2,ACCUM3,ACCUM4,ACCUM5,ACCUM6,ACCUM7,ACCUM8,
ACCUM9,ACCUM10,ACCUM11,ACCUM12,ACCUM13,ACCUM14,ACCUM15,ACCUM16,ACCUM17,
ACCUM18,ACCUM19,ACCUM20,ACCUM21,ACCUM22,ACCUM23,ACCUM24,ACCUM25,ACCUM26,
ACCUM27,ACCUM28,ACCUM29,ACCUM30,ACCUM31,ACCUM32,ACCUM33,OVERFLOW) is black-box
{
property REG_INPUTA_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTA_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTA_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTB_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTB_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTB_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_OUTPUT_CLK {“CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_OUTPUT_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_OUTPUT_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_SIGNEDAB_0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_SIGNEDAB_0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_SIGNEDAB_0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_SIGNEDAB_1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_SIGNEDAB_1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_SIGNEDAB_1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ADDNSUB_0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_ADDNSUB_0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_ADDNSUB_0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ADDNSUB_1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_ADDNSUB_1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_ADDNSUB_1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ACCUMSLOAD_0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_ACCUMSLOAD_0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_ACCUMSLOAD_0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ACCUMSLOAD_1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};