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参数资料
| 型号： | M2V56S30ATP-6 |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 X 0.875 INCH, TSOP2-54 |
| 文件页数： | 11/51页 |
| 文件大小： | 430K |
| 代理商： | M2V56S30ATP-6 |
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19
MITSUBISHI ELECTRIC
May '02
MITSUBISHI LSIs
SDRAM (Rev.1.41)
Single Data Rate
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
WRITE
A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4),
A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length
to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst
Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD.
From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is
high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE,
PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal
precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL
+ tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be
met.
ACT
PRE
ACT
Xa
0
Xa
00
Xa
Write (BL=4)
Write
Ya
0
00
Da0
Da1
Da2
Da3
ACT
Xa
00
Xa
Write with Auto-Precharge (BL=4)
Write
Ya
1
00
Da0
Da1
Da2
Da3
internal precharge starts
tRCD
tRP
BL
tWR
tRCD
tRP
BL
tWR
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M2V56S30ATP-7 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30ATP-8 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-6 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-7 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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