参数资料
型号: M2V56S30ATP-6
元件分类: DRAM
英文描述: 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封装: 0.400 X 0.875 INCH, TSOP2-54
文件页数: 14/51页
文件大小: 430K
代理商: M2V56S30ATP-6
21
MITSUBISHI ELECTRIC
May '02
MITSUBISHI LSIs
SDRAM (Rev.1.41)
Single Data Rate
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP
CLK
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
CL=2
CL=3
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is
minimum 1 CLK.
A PRE command to output disable latency is equivalent to the /CAS Latency.
Read Interrupted by Precharge (BL=4)
PRE
READ
Q0
Q1
Q2
PRE
READ
Q0
Q1
PRE
READ
Q0
PRE
READ
Q0
Q1
Q2
PRE
READ
Q0
Q1
PRE
READ
Q0
相关PDF资料
PDF描述
M30-6000206 2 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT
M30-6000406 4 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT
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M30-6011006 20 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT
M30-6011506 30 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT
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