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参数资料
| 型号： | M2V56S30ATP-6 |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 X 0.875 INCH, TSOP2-54 |
| 文件页数： | 16/51页 |
| 文件大小： | 430K |
| 代理商： | M2V56S30ATP-6 |
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23
MITSUBISHI ELECTRIC
May '02
MITSUBISHI LSIs
SDRAM (Rev.1.41)
Single Data Rate
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
Write Interrupted by Write (BL=4)
Write
Yb
0
00
Dc0
Dc1
Dc2
Dc3
Write
Ya
0
00
Da0
Da1
Da2
Db0
Write
Yc
0
10
ACT
Xa
00
Write Interrupted by Read (CL=2, BL=4)
READ
Yb
0
00
Da0
Da1
Qb0
Write
Ya
0
00
Qb1
Qb2
Qb3
don't care
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相关代理商/技术参数 |
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|---|---|
| M2V56S30ATP-7 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30ATP-8 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-6 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S30TP-7 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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