- 您现在的位置：买卖IC网 > PDF目录180205 > M393B5273CH0-CK0 512M X 72 MULTI DEVICE DRAM MODULE, 0.225 ns, DMA240 PDF资料下载
参数资料
| 型号： | M393B5273CH0-CK0 |
| 元件分类： | DRAM |
| 英文描述： | 512M X 72 MULTI DEVICE DRAM MODULE, 0.225 ns, DMA240 |
| 封装： | HALOGEN FREE AND ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 21/58页 |
| 文件大小： | 1982K |
| 代理商： | M393B5273CH0-CK0 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页
- 22 -
datasheet
DDR3 SDRAM
Rev. 1.0
Registered DIMM
14. AC & DC Output Measurement Levels
14.1 Single Ended AC and DC Output Levels
[ Table 8 ] Single Ended AC and DC output levels
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25
Ω to VTT=VDDQ/2.
14.2 Differential AC and DC Output Levels
[ Table 9 ] Differential AC and DC output levels
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25
Ω to VTT=VDDQ/2 at each of the differential outputs.
14.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
[ Table 10 ] Single ended Output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 11 ] Single ended output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
Figure 6. Single-ended output slew rate definition
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC) DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC) DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC) AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V1
VOL(AC) AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V1
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V1
Description
Measured
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
VOH(AC)-VOL(AC)
Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
VOH(AC)-VOL(AC)
Delta TFse
Parameter
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Min
Max
Min
Max
Min
Max
Min
Max
Single ended output slew rate
SRQse
2.5
5
2.5
5
2.5
5
TBD
5
V/ns
VOHdiff(AC)
VOLdiff(AC)
delta
TRdiff
delta
TFdiff
VTT
相关PDF资料 |
PDF描述 |
|---|---|
| M393B5773CH0-CK0 | 256M X 72 MULTI DEVICE DRAM MODULE, 0.225 ns, DMA240 |
| M3950/1529A012 | TOGGLE SWITCH, 3PDT, LATCHED, 4A, 28VDC, THROUGH HOLE-STRAIGHT |
| M83731/2327D110 | TOGGLE SWITCH, 3PDT, MOMENTARY, 4A, 28VDC, THROUGH HOLE-STRAIGHT |
| M3950/1726A110 | TOGGLE SWITCH, 3PDT, LATCHED, 4A, 28VDC, THROUGH HOLE-STRAIGHT |
| M3E-R21ZQXFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.5 MHz - 155.52 MHz, PECL OUTPUT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M393B5273CH0-CK004 | 制造商:Samsung 功能描述:4GBYTE REGISTERED DIMM, DDR3-1600 - Trays |
| M393B5273DH-CH9E8 | 制造商:Samsung Semiconductor 功能描述:4GB 2RX8 PC3-8500R-07-00-B0-D1 - Trays |
| M393B5670EH1 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR3 SDRAM Memory |
| M393B5670EH1-CF801 | 制造商:Samsung Semiconductor 功能描述:2GB DDR3 REGISTERED DIMM, 1066MHZ, - Trays |
| M393B5670EH1-CH904 | 制造商:Samsung Semiconductor 功能描述:2GBYTE REGISTERED DIMM,DDR3-1333 - Trays |
发布紧急采购，3分钟左右您将得到回复。