PWM Register Descriptions
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
129
11.2.2 PWM Clock Select and Polarity Register
Read: Anytime
Write: Anytime
PCLK3 — PWM Channel 3 Clock Select Bit
0 = Clock B is the clock source for channel 3.
1 = Clock S1 is the clock source for channel 3.
PCLK2 — PWM Channel 2 Clock Select Bit
0 = Clock B is the clock source for channel 2.
1 = Clock S1 is the clock source for channel 2.
PCLK1 — PWM Channel 1 Clock Select Bit
0 = Clock A is the clock source for channel 1.
1 = Clock S0 is the clock source for channel 1.
PCLK0 — PWM Channel 0 Clock Select Bit
0 = Clock A is the clock source for channel 0.
1 = Clock S0 is the clock source for channel 0.
If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse may
occur during the transition.
PPOL3 — PWM Channel 3 Polarity Bit
0 = Channel 3 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 3 output is high at the beginning of the period, low when the duty count is reached.
PPOL2 — PWM Channel 2 Polarity Bit
0 = Channel 2 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 2 output is high at the beginning of the period, low when the duty count is reached.
PPOL1 — PWM Channel 1 Polarity Bit
0 = Channel 1 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 1 output is high at the beginning of the period, low when the duty count is reached.
PPOL0 — PWM Channel 0 Polarity Bit
0 = Channel 0 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 0 output is high at the beginning of the period, low when the duty count is reached.
Depending on the polarity bit, the duty registers may contain the count of either the high time or the low
time. If the polarity bit is 0 and left alignment is selected, the duty registers contain a count of the low time.
If the polarity bit is 1, the duty registers contain a count of the high time.
Address: $0041
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PCLK3
PCLK2
PCLK1
PCLK0
PPOL3
PPOL2
PPOL1
PPOL0
0
0
0
0
0
0
0
0
Figure 11-5. PWM Clock Select and Polarity Register (PWPOL)