Timer Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
183
By setting TFMOD in queue mode, when NOVW bit is set and the corresponding capture and holding
registers are emptied, an input capture event will first update the related input capture register with the
main timer contents. At the next event, the TCn data is transferred to the TCnH register, the TCn is
updated, and the CnF interrupt flag is set. See
Figure 13-19
. In all other input capture cases, the
interrupt flag is set by a valid external event on PTn.
0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid input capture transition on the
corresponding port pin occurs.
1 = If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F–C0F in TFLG1 ($8E) are set
only when a latch on the corresponding holding register occurs. If the queue mode is not
engaged, the timer flags C3F–C0F are set the same way as for TFMOD = 0.
PACMX — 8-Bit Pulse Accumulators Maximum Count Bit
0 = Normal operation. When the 8-bit pulse accumulator has reached the value $FF, with the next
active edge, it will be incremented to $00.
1 = When the 8-bit pulse accumulator has reached the value $FF, it will not be incremented further.
The value $FF indicates a count of 255 or more.
BUFEN
—
IC Buffer Enable Bit
0 = Input capture and pulse accumulator holding registers are disabled.
1 = Input capture and pulse accumulator holding registers are enabled. The latching mode is
defined by LATQ control bit. Writing a 1 into ICLAT bit in MCCTL ($A6) when LATQ is set, will
produce latching of input capture and pulse accumulator registers into their holding registers.
LATQ — Input Control Latch or Queue Mode Enable Bit
The BUFEN control bit should be set to enable the IC and pulse accumulators’ holding registers.
Otherwise, LATQ latching modes are disabled.
Writing one into ICLAT bit in MCCTL ($A6), when LATQ and BUFEN are set will produce latching of
input capture and pulse accumulators registers into their holding registers.
0 = Queue mode of input capture is enabled. The main timer value is memorized in the IC register
by a valid input pin transition. With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register memorizes the new timer value.
1 = Latch mode is enabled. Latching function occurs when modulus down-counter reaches 0 or a 0
is written into the count register MCCNT (see
13.3.1.2 Buffered IC Channels
). With a latching
event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding
registers. The 8-bit pulse accumulators are cleared.
13.4.20 Timer Test Register
Read: Anytime
Write: Only in special mode (SMOD = 1)
Address: $00AD
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 0
Read:
Write:
Reset:
TCBYP
PCBYP
(1)
0
0
0
0
0
0
0
0
= Unimplemented
1. Available only on MC68HC912B32 devices.
Figure 13-41. Timer Test Register (TIMTST)