BDLC Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
231
The BDLC cannot transmit a BREAK symbol. It can receive a BREAK symbol only from the J1850 bus.
15.8.5.5 Summary
Table 15-1
provides a bus error summary.
15.9 BDLC Registers
Eight registers are available for controlling operation of the BDLC and for communicating data and status
information. A full description of each register is given here.
15.9.1 BDLC Control Register 1
IMSG — Ignore Message Bit
This bit disables the receiver until a new start-of-frame (SOF) is detected. The bit is cleared
automatically by the reception of an SOF symbol or a BREAK symbol. It then generates interrupt
requests and allows changes of the status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit. When set, all BDLC interrupt requests are masked (except $20
in BSVR) and the status bits are held in their reset state. If this bit is set while the BDLC is receiving a
message, the rest of the incoming message is ignored.
1 = Disable receiver
0 = Enable receiver
Table 15-1. BDLC J1850 Bus Error Summary
Error Condition
BDLC Function
Transmission error
For invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt
is generated. BDLC stops transmission.
Cyclical redundancy check
(CRC) error
CRC error interrupt is generated.
BDLC waits for EOF.
Invalid symbol: BDLC transmits,
but receives invalid bits (noise)
The BDLC aborts transmission immediately. Invalid symbol interrupt is generated.
Framing error
Invalid symbol interrupt is generated. BDLC waits for end of frame (EOF).
Bus short to V
DD
The BDLC does not transmit until the bus is idle. Invalid symbol interrupt is generated.
EOF interrupt also must be seen before another transmission attempt. Depending on
length of the short, LOA flag also may be set.
Bus short to GND
Thermal overload shuts down physical interface. Fault condition is seen as invalid
symbol flag. EOF interrupt must also be seen before another transmission attempt.
BDLC receives BREAK symbol
Invalid symbol interrupt is generated. BDLC waits for the next valid SOF.
Address: $00F8
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IMSG
CLKS
R1
R0
0
0
IE
WCM
Write:
R
R
Reset:
1
1
1
0
0
0
0
0
R
= Reserved
Figure 15-12. BDLC Control Register 1 (BCR1)